mirror of https://github.com/proxmox/mirror_qemu
pci: Make errp the last parameter of pci_add_capability()
Add Error argument for pci_add_capability() to leverage the errp to pass info on errors. This way is helpful for its callers to make a better error handling when moving to 'realize'. Cc: pbonzini@redhat.com Cc: rth@twiddle.net Cc: ehabkost@redhat.com Cc: mst@redhat.com Cc: jasowang@redhat.com Cc: marcel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>master
parent
9a815774bb
commit
9a7c2a5970
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@ -1158,13 +1158,23 @@ static void amdvi_realize(DeviceState *dev, Error **err)
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x86_iommu->type = TYPE_AMD;
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x86_iommu->type = TYPE_AMD;
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qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);
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qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);
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object_property_set_bool(OBJECT(&s->pci), true, "realized", err);
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object_property_set_bool(OBJECT(&s->pci), true, "realized", err);
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s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
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ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,
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AMDVI_CAPAB_SIZE);
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AMDVI_CAPAB_SIZE, err);
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assert(s->capab_offset > 0);
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if (ret < 0) {
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ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE);
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return;
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assert(ret > 0);
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}
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ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE);
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s->capab_offset = ret;
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assert(ret > 0);
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ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0,
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AMDVI_CAPAB_REG_SIZE, err);
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if (ret < 0) {
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return;
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}
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ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0,
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AMDVI_CAPAB_REG_SIZE, err);
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if (ret < 0) {
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return;
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}
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/* set up MMIO */
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/* set up MMIO */
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memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
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memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
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@ -47,6 +47,7 @@
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#include "e1000e_core.h"
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#include "e1000e_core.h"
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#include "trace.h"
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#include "trace.h"
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#include "qapi/error.h"
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#define TYPE_E1000E "e1000e"
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#define TYPE_E1000E "e1000e"
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#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
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#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
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@ -372,9 +373,15 @@ e1000e_gen_dsn(uint8_t *mac)
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static int
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static int
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e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
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e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
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{
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{
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int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF);
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Error *local_err = NULL;
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int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
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PCI_PM_SIZEOF, &local_err);
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if (local_err) {
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error_report_err(local_err);
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return ret;
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}
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if (ret > 0) {
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pci_set_word(pdev->config + offset + PCI_PM_PMC,
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pci_set_word(pdev->config + offset + PCI_PM_PMC,
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PCI_PM_CAP_VER_1_1 |
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PCI_PM_CAP_VER_1_1 |
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pmc);
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pmc);
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@ -386,7 +393,6 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
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pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
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pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
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PCI_PM_CTRL_PME_STATUS);
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PCI_PM_CTRL_PME_STATUS);
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}
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return ret;
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return ret;
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}
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}
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@ -48,6 +48,7 @@
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#include "sysemu/sysemu.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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#include "sysemu/dma.h"
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#include "qemu/bitops.h"
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#include "qemu/bitops.h"
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#include "qapi/error.h"
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/* QEMU sends frames smaller than 60 bytes to ethernet nics.
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/* QEMU sends frames smaller than 60 bytes to ethernet nics.
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* Such frames are rejected by real nics and their emulations.
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* Such frames are rejected by real nics and their emulations.
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@ -494,7 +495,7 @@ static void eepro100_fcp_interrupt(EEPRO100State * s)
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}
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}
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#endif
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#endif
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static void e100_pci_reset(EEPRO100State * s)
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static void e100_pci_reset(EEPRO100State *s, Error **errp)
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{
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{
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E100PCIDeviceInfo *info = eepro100_get_class(s);
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E100PCIDeviceInfo *info = eepro100_get_class(s);
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uint32_t device = s->device;
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uint32_t device = s->device;
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@ -570,8 +571,12 @@ static void e100_pci_reset(EEPRO100State * s)
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/* Power Management Capabilities */
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/* Power Management Capabilities */
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int cfg_offset = 0xdc;
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int cfg_offset = 0xdc;
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int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
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int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
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cfg_offset, PCI_PM_SIZEOF);
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cfg_offset, PCI_PM_SIZEOF,
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assert(r > 0);
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errp);
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if (r < 0) {
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return;
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}
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pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
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pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
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#if 0 /* TODO: replace dummy code for power management emulation. */
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#if 0 /* TODO: replace dummy code for power management emulation. */
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/* TODO: Power Management Control / Status. */
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/* TODO: Power Management Control / Status. */
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@ -1858,12 +1863,17 @@ static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
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{
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{
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EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
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EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
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E100PCIDeviceInfo *info = eepro100_get_class(s);
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E100PCIDeviceInfo *info = eepro100_get_class(s);
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Error *local_err = NULL;
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TRACE(OTHER, logout("\n"));
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TRACE(OTHER, logout("\n"));
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s->device = info->device;
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s->device = info->device;
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e100_pci_reset(s);
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e100_pci_reset(s, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
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/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
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* i82559 and later support 64 or 256 word EEPROM. */
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* i82559 and later support 64 or 256 word EEPROM. */
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@ -44,6 +44,7 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "hw/i386/ich9.h"
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#include "hw/i386/ich9.h"
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#include "qapi/error.h"
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/*****************************************************************************/
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/*****************************************************************************/
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10
hw/pci/pci.c
10
hw/pci/pci.c
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@ -2264,15 +2264,13 @@ static void pci_del_option_rom(PCIDevice *pdev)
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* in pci config space
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* in pci config space
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*/
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*/
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int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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uint8_t offset, uint8_t size)
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uint8_t offset, uint8_t size,
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Error **errp)
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{
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{
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int ret;
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int ret;
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Error *local_err = NULL;
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ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
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ret = pci_add_capability2(pdev, cap_id, offset, size, errp);
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if (ret < 0) {
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error_report_err(local_err);
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}
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return ret;
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return ret;
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}
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}
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@ -33,6 +33,7 @@
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bus.h"
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#include "qemu/range.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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/* PCI bridge subsystem vendor ID helper functions */
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/* PCI bridge subsystem vendor ID helper functions */
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#define PCI_SSVID_SIZEOF 8
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#define PCI_SSVID_SIZEOF 8
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@ -43,8 +44,12 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
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uint16_t svid, uint16_t ssid)
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uint16_t svid, uint16_t ssid)
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{
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{
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int pos;
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int pos;
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pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
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Error *local_err = NULL;
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pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
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PCI_SSVID_SIZEOF, &local_err);
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if (pos < 0) {
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if (pos < 0) {
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error_report_err(local_err);
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return pos;
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return pos;
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}
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}
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@ -91,11 +91,14 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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/* PCIe cap v2 init */
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/* PCIe cap v2 init */
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int pos;
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int pos;
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uint8_t *exp_cap;
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uint8_t *exp_cap;
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Error *local_err = NULL;
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assert(pci_is_express(dev));
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF);
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
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PCI_EXP_VER2_SIZEOF, &local_err);
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if (pos < 0) {
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if (pos < 0) {
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error_report_err(local_err);
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return pos;
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return pos;
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}
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}
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dev->exp.exp_cap = pos;
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dev->exp.exp_cap = pos;
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@ -123,11 +126,14 @@ int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
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{
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{
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/* PCIe cap v1 init */
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/* PCIe cap v1 init */
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int pos;
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int pos;
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Error *local_err = NULL;
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assert(pci_is_express(dev));
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF);
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
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PCI_EXP_VER1_SIZEOF, &local_err);
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if (pos < 0) {
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if (pos < 0) {
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error_report_err(local_err);
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return pos;
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return pos;
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}
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}
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dev->exp.exp_cap = pos;
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dev->exp.exp_cap = pos;
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@ -450,9 +450,12 @@ static int shpc_cap_add_config(PCIDevice *d)
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{
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{
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uint8_t *config;
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uint8_t *config;
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int config_offset;
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int config_offset;
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Error *local_err = NULL;
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config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
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config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
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0, SHPC_CAP_LENGTH);
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0, SHPC_CAP_LENGTH,
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&local_err);
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if (config_offset < 0) {
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if (config_offset < 0) {
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error_report_err(local_err);
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return config_offset;
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return config_offset;
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}
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}
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config = d->config + config_offset;
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config = d->config + config_offset;
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@ -2,6 +2,7 @@
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#include "hw/pci/slotid_cap.h"
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#include "hw/pci/slotid_cap.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "qemu/error-report.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#define SLOTID_CAP_LENGTH 4
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#define SLOTID_CAP_LENGTH 4
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#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
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#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
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@ -11,6 +12,8 @@ int slotid_cap_init(PCIDevice *d, int nslots,
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unsigned offset)
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unsigned offset)
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{
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{
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int cap;
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int cap;
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Error *local_err = NULL;
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if (!chassis) {
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if (!chassis) {
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error_report("Bridge chassis not specified. Each bridge is required "
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error_report("Bridge chassis not specified. Each bridge is required "
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"to be assigned a unique chassis id > 0.");
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"to be assigned a unique chassis id > 0.");
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@ -21,8 +24,10 @@ int slotid_cap_init(PCIDevice *d, int nslots,
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return -EINVAL;
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return -EINVAL;
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}
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}
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cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH);
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cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset,
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SLOTID_CAP_LENGTH, &local_err);
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if (cap < 0) {
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if (cap < 0) {
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error_report_err(local_err);
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return cap;
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return cap;
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}
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}
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/* We make each chassis unique, this way each bridge is First in Chassis */
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/* We make each chassis unique, this way each bridge is First in Chassis */
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@ -1743,11 +1743,14 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
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PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
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PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
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}
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}
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pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size);
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pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size,
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if (pos > 0) {
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errp);
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vdev->pdev.exp.exp_cap = pos;
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if (pos < 0) {
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return pos;
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}
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}
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vdev->pdev.exp.exp_cap = pos;
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return pos;
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return pos;
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}
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}
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@ -1162,8 +1162,8 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
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PCIDevice *dev = &proxy->pci_dev;
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PCIDevice *dev = &proxy->pci_dev;
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int offset;
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int offset;
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offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len);
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offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
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assert(offset > 0);
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cap->cap_len, &error_abort);
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assert(cap->cap_len >= sizeof *cap);
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assert(cap->cap_len >= sizeof *cap);
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memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
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memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
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@ -1810,8 +1810,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
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pos = pcie_endpoint_cap_init(pci_dev, 0);
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pos = pcie_endpoint_cap_init(pci_dev, 0);
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assert(pos > 0);
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assert(pos > 0);
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pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);
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pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
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assert(pos > 0);
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PCI_PM_SIZEOF, errp);
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if (pos < 0) {
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return;
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}
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pci_dev->exp.pm_cap = pos;
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pci_dev->exp.pm_cap = pos;
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/*
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/*
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@ -356,7 +356,8 @@ void pci_unregister_vga(PCIDevice *pci_dev);
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pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
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pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
|
||||||
|
|
||||||
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
||||||
uint8_t offset, uint8_t size);
|
uint8_t offset, uint8_t size,
|
||||||
|
Error **errp);
|
||||||
int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
|
int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
|
||||||
uint8_t offset, uint8_t size,
|
uint8_t offset, uint8_t size,
|
||||||
Error **errp);
|
Error **errp);
|
||||||
|
|
Loading…
Reference in New Issue