mirror of https://github.com/proxmox/mirror_qemu
target/arm: Implement HCR.DC
The HCR.DC virtualization configuration register bit has the following effects: * SCTLR.M behaves as if it is 0 for all purposes except direct reads of the bit * HCR.VM behaves as if it is 1 for all purposes except direct reads of the bit * the memory type produced by the first stage of the EL1&EL0 translation regime is Normal Non-Shareable, Inner Write-Back Read-Allocate Write-Allocate, Outer Write-Back Read-Allocate Write-Allocate. Implement this behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181012144235.19646-5-peter.maydell@linaro.orgmaster
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b4ab8ce98b
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9d1bab337c
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@ -2303,13 +2303,15 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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* * The Non-secure TTBCR.EAE bit is set to 1
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* * The implementation includes EL2, and the value of HCR.VM is 1
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*
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* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
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*
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* ATS1Hx always uses the 64bit format (not supported yet).
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*/
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format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
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format64 |= env->cp15.hcr_el2 & HCR_VM;
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format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
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} else {
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format64 |= arm_current_el(env) == 2;
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}
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@ -8718,7 +8720,8 @@ static inline bool regime_translation_disabled(CPUARMState *env,
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}
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if (mmu_idx == ARMMMUIdx_S2NS) {
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return (env->cp15.hcr_el2 & HCR_VM) == 0;
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/* HCR.DC means HCR.VM behaves as 1 */
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return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
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}
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if (env->cp15.hcr_el2 & HCR_TGE) {
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@ -8728,6 +8731,12 @@ static inline bool regime_translation_disabled(CPUARMState *env,
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}
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}
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if ((env->cp15.hcr_el2 & HCR_DC) &&
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(mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) {
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/* HCR.DC means SCTLR_EL1.M behaves as 0 */
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return true;
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}
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return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
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}
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@ -10708,6 +10717,16 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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/* Combine the S1 and S2 cache attributes, if needed */
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if (!ret && cacheattrs != NULL) {
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if (env->cp15.hcr_el2 & HCR_DC) {
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/*
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* HCR.DC forces the first stage attributes to
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* Normal Non-Shareable,
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* Inner Write-Back Read-Allocate Write-Allocate,
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* Outer Write-Back Read-Allocate Write-Allocate.
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*/
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cacheattrs->attrs = 0xff;
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cacheattrs->shareability = 0;
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}
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*cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
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}
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