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esp: support 24-bit DMA 

SeaBIOS will issue requests for more than 64k when loading a CD-ROM
image into memory.  Support the TCHI register from the AMD PCscsi
spec.

Acked-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
master
Paolo Bonzini 2012-08-02 15:43:39 +02:00
parent fb6541571e
commit 9ea73f8b10
1 changed files with 11 additions and 5 deletions
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16
hw/esp.c
View File

@ -87,7 +87,9 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf)
target = s->wregs[ESP_WBUSID] & BUSID_DID; target = s->wregs[ESP_WBUSID] & BUSID_DID;
if (s->dma) { if (s->dma) {
dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); dmalen = s->rregs[ESP_TCLO];
dmalen |= s->rregs[ESP_TCMID] << 8;
dmalen |= s->rregs[ESP_TCHI] << 16;
s->dma_memory_read(s->dma_opaque, buf, dmalen); s->dma_memory_read(s->dma_opaque, buf, dmalen);
} else { } else {
dmalen = s->ti_size; dmalen = s->ti_size;
@ -226,6 +228,7 @@ static void esp_dma_done(ESPState *s)
s->rregs[ESP_RFLAGS] = 0; s->rregs[ESP_RFLAGS] = 0;
s->rregs[ESP_TCLO] = 0; s->rregs[ESP_TCLO] = 0;
s->rregs[ESP_TCMID] = 0; s->rregs[ESP_TCMID] = 0;
s->rregs[ESP_TCHI] = 0;
esp_raise_irq(s); esp_raise_irq(s);
} }
@ -328,7 +331,9 @@ static void handle_ti(ESPState *s)
return; return;
} }
dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); dmalen = s->rregs[ESP_TCLO];
dmalen |= s->rregs[ESP_TCMID] << 8;
dmalen |= s->rregs[ESP_TCHI] << 16;
if (dmalen==0) { if (dmalen==0) {
dmalen=0x10000; dmalen=0x10000;
} }
@ -429,6 +434,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
switch (saddr) { switch (saddr) {
case ESP_TCLO: case ESP_TCLO:
case ESP_TCMID: case ESP_TCMID:
case ESP_TCHI:
s->rregs[ESP_RSTAT] &= ~STAT_TC; s->rregs[ESP_RSTAT] &= ~STAT_TC;
break; break;
case ESP_FIFO: case ESP_FIFO:
@ -448,6 +454,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
/* Reload DMA counter. */ /* Reload DMA counter. */
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
} else { } else {
s->dma = 0; s->dma = 0;
} }
@ -530,13 +537,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
case ESP_WBUSID ... ESP_WSYNO: case ESP_WBUSID ... ESP_WSYNO:
break; break;
case ESP_CFG1: case ESP_CFG1:
case ESP_CFG2: case ESP_CFG3:
case ESP_RES3: case ESP_RES4:
s->rregs[saddr] = val; s->rregs[saddr] = val;
break; break;
case ESP_WCCF ... ESP_WTEST: case ESP_WCCF ... ESP_WTEST:
break; break;
case ESP_CFG2 ... ESP_RES4:
s->rregs[saddr] = val;
break;
default: default:
trace_esp_error_invalid_write(val, saddr); trace_esp_error_invalid_write(val, saddr);
return; return;