mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: Add SIMD three-different multiply accumulate insns
Add support for the multiply-accumulate instructions from the SIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts * framework for handling the 64x64->128 widening subpart * implementation of the multiply-accumulate instructions SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2, UMULL, UMULL2, SMULL, SMULL2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>master
Peter Maydell
parent
901ad5259f
commit
a08582f41e
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@ -700,6 +700,9 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
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* zero extend as we are filling a partial chunk of the vector register.
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* These functions don't support 128 bit loads/stores, which would be
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* normal load/store operations.
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*
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* The _i32 versions are useful when operating on 32 bit quantities
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* (eg for floating point single or using Neon helper functions).
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*/
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/* Get value of an element within a vector register */
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@ -735,6 +738,32 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
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}
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}
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static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
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int element, TCGMemOp memop)
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{
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int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
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switch (memop) {
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case MO_8:
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tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
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break;
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case MO_16:
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tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
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break;
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case MO_8|MO_SIGN:
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tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
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break;
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case MO_16|MO_SIGN:
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tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
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break;
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case MO_32:
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case MO_32|MO_SIGN:
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tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* Set value of an element within a vector register */
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static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
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int element, TCGMemOp memop)
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@ -5518,6 +5547,150 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
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int opcode, int rd, int rn, int rm)
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{
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/* 3-reg-different widening insns: 64 x 64 -> 128 */
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TCGv_i64 tcg_res[2];
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int pass, accop;
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tcg_res[0] = tcg_temp_new_i64();
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tcg_res[1] = tcg_temp_new_i64();
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/* Does this op do an adding accumulate, a subtracting accumulate,
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* or no accumulate at all?
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*/
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switch (opcode) {
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case 5:
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case 8:
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case 9:
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accop = 1;
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break;
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case 10:
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case 11:
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accop = -1;
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break;
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default:
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accop = 0;
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break;
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}
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if (accop != 0) {
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read_vec_element(s, tcg_res[0], rd, 0, MO_64);
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read_vec_element(s, tcg_res[1], rd, 1, MO_64);
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}
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/* size == 2 means two 32x32->64 operations; this is worth special
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* casing because we can generally handle it inline.
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*/
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if (size == 2) {
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for (pass = 0; pass < 2; pass++) {
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TCGv_i64 tcg_op1 = tcg_temp_new_i64();
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TCGv_i64 tcg_op2 = tcg_temp_new_i64();
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TCGv_i64 tcg_passres;
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TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
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int elt = pass + is_q * 2;
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read_vec_element(s, tcg_op1, rn, elt, memop);
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read_vec_element(s, tcg_op2, rm, elt, memop);
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if (accop == 0) {
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tcg_passres = tcg_res[pass];
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} else {
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tcg_passres = tcg_temp_new_i64();
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}
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switch (opcode) {
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case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
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case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
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case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
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tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
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break;
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default:
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g_assert_not_reached();
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}
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if (accop > 0) {
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tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
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tcg_temp_free_i64(tcg_passres);
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} else if (accop < 0) {
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tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
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tcg_temp_free_i64(tcg_passres);
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}
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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}
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} else {
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/* size 0 or 1, generally helper functions */
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for (pass = 0; pass < 2; pass++) {
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TCGv_i32 tcg_op1 = tcg_temp_new_i32();
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TCGv_i32 tcg_op2 = tcg_temp_new_i32();
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TCGv_i64 tcg_passres;
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int elt = pass + is_q * 2;
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read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
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read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
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if (accop == 0) {
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tcg_passres = tcg_res[pass];
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} else {
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tcg_passres = tcg_temp_new_i64();
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}
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switch (opcode) {
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case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
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case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
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case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
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if (size == 0) {
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if (is_u) {
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gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
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} else {
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gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
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}
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} else {
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if (is_u) {
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gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
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} else {
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gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
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}
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}
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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if (accop > 0) {
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if (size == 0) {
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gen_helper_neon_addl_u16(tcg_res[pass], tcg_res[pass],
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tcg_passres);
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} else {
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gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
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tcg_passres);
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}
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tcg_temp_free_i64(tcg_passres);
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} else if (accop < 0) {
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if (size == 0) {
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gen_helper_neon_subl_u16(tcg_res[pass], tcg_res[pass],
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tcg_passres);
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} else {
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gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
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tcg_passres);
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}
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tcg_temp_free_i64(tcg_passres);
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}
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}
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}
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write_vec_element(s, tcg_res[0], rd, 0, MO_64);
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write_vec_element(s, tcg_res[1], rd, 1, MO_64);
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tcg_temp_free_i64(tcg_res[0]);
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tcg_temp_free_i64(tcg_res[1]);
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}
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/* C3.6.15 AdvSIMD three different
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* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+------+--------+-----+------+------+
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@ -5526,7 +5699,65 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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*/
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static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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/* Instructions in this group fall into three basic classes
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* (in each case with the operation working on each element in
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* the input vectors):
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* (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
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* 128 bit input)
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* (2) wide 64 x 128 -> 128
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* (3) narrowing 128 x 128 -> 64
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* Here we do initial decode, catch unallocated cases and
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* dispatch to separate functions for each class.
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*/
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int is_q = extract32(insn, 30, 1);
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int is_u = extract32(insn, 29, 1);
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int size = extract32(insn, 22, 2);
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int opcode = extract32(insn, 12, 4);
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int rm = extract32(insn, 16, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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switch (opcode) {
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case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
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case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
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/* 64 x 128 -> 128 */
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unsupported_encoding(s, insn);
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break;
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case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
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case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
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/* 128 x 128 -> 64 */
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unsupported_encoding(s, insn);
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break;
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case 9:
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case 11:
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case 13:
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case 14:
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if (is_u) {
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unallocated_encoding(s);
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return;
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}
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/* fall through */
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case 0:
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case 2:
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case 5:
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case 7:
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unsupported_encoding(s, insn);
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break;
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case 8:
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case 10:
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case 12:
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/* 64 x 64 -> 128 */
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if (size == 3) {
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unallocated_encoding(s);
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return;
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}
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handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
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break;
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default:
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/* opcode 15 not allocated */
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unallocated_encoding(s);
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break;
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}
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}
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/* C3.6.16 AdvSIMD three same
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