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target-alpha: fix bug: integer conditional branch offset is 21 bits wide. 

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6924 c046a42c-6fe2-441c-8c8c-71466251a162
master
aurel32 2009-03-29 00:13:56 +00:00
parent 577d5e7fe2
commit a151674462
1 changed files with 10 additions and 10 deletions
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20
target-alpha/translate.c
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@ -290,7 +290,7 @@ static always_inline void gen_store_mem (DisasContext *ctx,
static always_inline void gen_bcond (DisasContext *ctx, static always_inline void gen_bcond (DisasContext *ctx,
TCGCond cond, TCGCond cond,
int ra, int32_t disp16, int mask) int ra, int32_t disp, int mask)
{ {
int l1, l2; int l1, l2;
@ -313,7 +313,7 @@ static always_inline void gen_bcond (DisasContext *ctx,
tcg_gen_movi_i64(cpu_pc, ctx->pc); tcg_gen_movi_i64(cpu_pc, ctx->pc);
tcg_gen_br(l2); tcg_gen_br(l2);
gen_set_label(l1); gen_set_label(l1);
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
gen_set_label(l2); gen_set_label(l2);
} }
@ -2285,42 +2285,42 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x38: case 0x38:
/* BLBC */ /* BLBC */
gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1); gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
ret = 1; ret = 1;
break; break;
case 0x39: case 0x39:
/* BEQ */ /* BEQ */
gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0); gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
case 0x3A: case 0x3A:
/* BLT */ /* BLT */
gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0); gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
case 0x3B: case 0x3B:
/* BLE */ /* BLE */
gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0); gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
case 0x3C: case 0x3C:
/* BLBS */ /* BLBS */
gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1); gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
ret = 1; ret = 1;
break; break;
case 0x3D: case 0x3D:
/* BNE */ /* BNE */
gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0); gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
case 0x3E: case 0x3E:
/* BGE */ /* BGE */
gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0); gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
case 0x3F: case 0x3F:
/* BGT */ /* BGT */
gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0); gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
ret = 1; ret = 1;
break; break;
invalid_opc: invalid_opc: