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target/ppc: Implemented remaining vector divide extended 

Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
vdiveuq: Vector Divide Extended Unsigned Quadword

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220525134954.85056-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
master
Lucas Mateus Castro (alqotel) 2022-05-25 10:49:52 -03:00 committed by Daniel Henrique Barboza
parent 62c9947fb7
commit a173ba88be
4 changed files with 76 additions and 0 deletions
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4
target/ppc/helper.h
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@ -177,6 +177,10 @@ DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVSQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVESD, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVEUD, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVESQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVEUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(vslo, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(vsro, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(vsrv, TCG_CALL_NO_RWG, void, avr, avr, avr)

4
target/ppc/insn32.decode
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@ -798,3 +798,7 @@ VDIVUQ 000100 ..... ..... ..... 00000001011 @VX
VDIVESW 000100 ..... ..... ..... 01110001011 @VX
VDIVEUW 000100 ..... ..... ..... 01010001011 @VX
VDIVESD 000100 ..... ..... ..... 01111001011 @VX
VDIVEUD 000100 ..... ..... ..... 01011001011 @VX
VDIVESQ 000100 ..... ..... ..... 01100001011 @VX
VDIVEUQ 000100 ..... ..... ..... 01000001011 @VX

64
target/ppc/int_helper.c
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@ -1183,6 +1183,70 @@ void helper_VDIVUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
}
}
void helper_VDIVESD(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
int64_t high;
uint64_t low;
for (i = 0; i < 2; i++) {
high = a->s64[i];
low = 0;
if (unlikely((high == INT64_MIN && b->s64[i] == -1) || !b->s64[i])) {
t->s64[i] = a->s64[i]; /* Undefined behavior */
} else {
divs128(&low, &high, b->s64[i]);
t->s64[i] = low;
}
}
}
void helper_VDIVEUD(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
uint64_t high, low;
for (i = 0; i < 2; i++) {
high = a->u64[i];
low = 0;
if (unlikely(!b->u64[i])) {
t->u64[i] = a->u64[i]; /* Undefined behavior */
} else {
divu128(&low, &high, b->u64[i]);
t->u64[i] = low;
}
}
}
void helper_VDIVESQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
{
Int128 high, low;
Int128 int128_min = int128_make128(0, INT64_MIN);
Int128 neg1 = int128_makes64(-1);
high = a->s128;
low = int128_zero();
if (unlikely(!int128_nz(b->s128) ||
(int128_eq(b->s128, neg1) && int128_eq(high, int128_min)))) {
t->s128 = a->s128; /* Undefined behavior */
} else {
divs256(&low, &high, b->s128);
t->s128 = low;
}
}
void helper_VDIVEUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
{
Int128 high, low;
high = a->s128;
low = int128_zero();
if (unlikely(!int128_nz(b->s128))) {
t->s128 = a->s128; /* Undefined behavior */
} else {
divu256(&low, &high, b->s128);
t->s128 = low;
}
}
void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;

4
target/ppc/translate/vmx-impl.c.inc
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@ -3367,6 +3367,10 @@ DIVU32(do_diveuw, do_diveu_i32)
TRANS_FLAGS2(ISA310, VDIVESW, do_vdiv_vmod, MO_32, do_divesw, NULL)
TRANS_FLAGS2(ISA310, VDIVEUW, do_vdiv_vmod, MO_32, do_diveuw, NULL)
TRANS_FLAGS2(ISA310, VDIVESD, do_vx_helper, gen_helper_VDIVESD)
TRANS_FLAGS2(ISA310, VDIVEUD, do_vx_helper, gen_helper_VDIVEUD)
TRANS_FLAGS2(ISA310, VDIVESQ, do_vx_helper, gen_helper_VDIVESQ)
TRANS_FLAGS2(ISA310, VDIVEUQ, do_vx_helper, gen_helper_VDIVEUQ)
#undef DIVS32
#undef DIVU32