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Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions 

Most of these are not modelled in QEMU, so save the overhead of
calling a helper.

The only exception is dczeroa.  It assigns to hex_dczero_addr, which
is handled during packet commit.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
master
Taylor Simpson 2023-04-10 09:09:41 -07:00
parent 111c529aa6
commit a305a17039
2 changed files with 27 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
target/hexagon/gen_tcg.h
View File

@ -487,6 +487,19 @@
#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
/* dczeroa clears the 32 byte cache line at the address given */
#define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE
/* In linux-user mode, these are not modelled, suppress compiler warning */
#define fGEN_TCG_Y2_dcinva(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_dccleaninva(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_dccleana(SHORTCODE) \
do { RsV = RsV; } while (0)
#define fGEN_TCG_Y2_icinva(SHORTCODE) \
do { RsV = RsV; } while (0)
/*
* dealloc_return
* Assembler mapped to
@ -1211,6 +1224,17 @@
do { \
RsV = RsV; \
} while (0)
#define fGEN_TCG_Y2_isync(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_barrier(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_syncht(SHORTCODE) \
do { } while (0)
#define fGEN_TCG_Y2_dcfetchbo(SHORTCODE) \
do { \
RsV = RsV; \
uiV = uiV; \
} while (0)
#define fGEN_TCG_J2_trap0(SHORTCODE) \
do { \

16
target/hexagon/macros.h
View File

@ -659,20 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
reg_field_info[FIELD].width, \
reg_field_info[FIELD].offset)
#define fBARRIER()
#define fSYNCH()
#define fISYNC()
#define fDCFETCH(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fICINVA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
#define fDCCLEANA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fDCCLEANINVA(REG) \
do { (void)REG; } while (0) /* Nothing to do in qemu */
#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
#ifdef QEMU_GENERATE
#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
#endif
#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
STRBITNUM) /* Nothing */