mirror of https://github.com/proxmox/mirror_qemu
Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <20231210220712.491494-5-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <bcain@quicinc.com>master
Taylor Simpson
Brian Cain
parent
c568919f98
commit
a3295f5436
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@ -23,181 +23,14 @@ import string
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import hex_common
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##
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## Helpers for gen_helper_function
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##
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def gen_decl_ea(f):
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f.write(" uint32_t EA;\n")
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def gen_helper_return_type(f, regtype, regid, regno):
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if regno > 1:
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f.write(", ")
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f.write("int32_t")
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def gen_helper_return_type_pair(f, regtype, regid, regno):
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if regno > 1:
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f.write(", ")
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f.write("int64_t")
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def gen_helper_arg(f, regtype, regid, regno):
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if regno > 0:
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f.write(", ")
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f.write(f"int32_t {regtype}{regid}V")
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def gen_helper_arg_new(f, regtype, regid, regno):
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if regno >= 0:
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f.write(", ")
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f.write(f"int32_t {regtype}{regid}N")
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def gen_helper_arg_pair(f, regtype, regid, regno):
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if regno >= 0:
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f.write(", ")
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f.write(f"int64_t {regtype}{regid}V")
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def gen_helper_arg_ext(f, regtype, regid, regno):
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if regno > 0:
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f.write(", ")
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f.write(f"void *{regtype}{regid}V_void")
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def gen_helper_arg_ext_pair(f, regtype, regid, regno):
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if regno > 0:
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f.write(", ")
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f.write(f"void *{regtype}{regid}V_void")
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def gen_helper_arg_opn(f, regtype, regid, i, tag):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_arg_ext_pair(f, regtype, regid, i)
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else:
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gen_helper_arg_pair(f, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_old_val(regtype, regid, tag):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_arg_ext(f, regtype, regid, i)
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else:
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gen_helper_arg(f, regtype, regid, i)
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elif hex_common.is_new_val(regtype, regid, tag):
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gen_helper_arg_new(f, regtype, regid, i)
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else:
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hex_common.bad_register(regtype, regid)
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else:
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hex_common.bad_register(regtype, regid)
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def gen_helper_arg_imm(f, immlett):
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f.write(f", int32_t {hex_common.imm_name(immlett)}")
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def gen_helper_dest_decl(f, regtype, regid, regno, subfield=""):
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f.write(f" int32_t {regtype}{regid}V{subfield} = 0;\n")
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def gen_helper_dest_decl_pair(f, regtype, regid, regno, subfield=""):
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f.write(f" int64_t {regtype}{regid}V{subfield} = 0;\n")
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def gen_helper_dest_decl_ext(f, regtype, regid):
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if regtype == "Q":
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f.write(
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f" /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}V_void) */\n"
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)
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else:
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f.write(
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f" /* {regtype}{regid}V is *(MMVector *)"
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f"({regtype}{regid}V_void) */\n"
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)
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def gen_helper_dest_decl_ext_pair(f, regtype, regid, regno):
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f.write(
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f" /* {regtype}{regid}V is *(MMVectorPair *))"
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f"{regtype}{regid}V_void) */\n"
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)
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def gen_helper_dest_decl_opn(f, regtype, regid, i):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_dest_decl_ext_pair(f, regtype, regid, i)
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else:
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gen_helper_dest_decl_pair(f, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_dest_decl_ext(f, regtype, regid)
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else:
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gen_helper_dest_decl(f, regtype, regid, i)
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else:
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hex_common.bad_register(regtype, regid)
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def gen_helper_src_var_ext(f, regtype, regid):
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if regtype == "Q":
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f.write(
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f" /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}V_void) */\n"
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)
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else:
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f.write(
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f" /* {regtype}{regid}V is *(MMVector *)"
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f"({regtype}{regid}V_void) */\n"
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)
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def gen_helper_src_var_ext_pair(f, regtype, regid, regno):
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f.write(
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f" /* {regtype}{regid}V{regno} is *(MMVectorPair *)"
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f"({regtype}{regid}V{regno}_void) */\n"
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)
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def gen_helper_return(f, regtype, regid, regno):
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f.write(f" return {regtype}{regid}V;\n")
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def gen_helper_return_pair(f, regtype, regid, regno):
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f.write(f" return {regtype}{regid}V;\n")
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def gen_helper_dst_write_ext(f, regtype, regid):
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return
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def gen_helper_dst_write_ext_pair(f, regtype, regid):
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return
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def gen_helper_return_opn(f, regtype, regid, i):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_dst_write_ext_pair(f, regtype, regid)
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else:
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gen_helper_return_pair(f, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_dst_write_ext(f, regtype, regid)
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else:
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gen_helper_return(f, regtype, regid, i)
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else:
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hex_common.bad_register(regtype, regid)
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##
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## Generate the TCG code to call the helper
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## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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## We produce:
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## int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t RtV)
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## {
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## uint32_t slot __attribute__(unused)) = 4;
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## int32_t RdV = 0;
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## { RdV=RsV+RtV;}
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## COUNT_HELPER(A2_add);
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## return RdV;
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## }
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##
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@ -205,151 +38,67 @@ def gen_helper_function(f, tag, tagregs, tagimms):
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regs = tagregs[tag]
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imms = tagimms[tag]
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numresults = 0
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numscalarresults = 0
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numscalarreadwrite = 0
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ret_type = hex_common.helper_ret_type(tag, regs).func_arg
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declared = []
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for arg in hex_common.helper_args(tag, regs, imms):
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declared.append(arg.func_arg)
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arguments = ", ".join(declared)
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f.write(f"{ret_type} HELPER({tag})({arguments})\n")
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f.write("{\n")
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if hex_common.need_ea(tag):
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f.write(hex_common.code_fmt(f"""\
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uint32_t EA;
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"""))
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## Declare the return variable
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if not hex_common.is_predicated(tag):
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for regtype, regid in regs:
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reg = hex_common.get_register(tag, regtype, regid)
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if reg.is_writeonly() and not reg.is_hvx_reg():
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f.write(hex_common.code_fmt(f"""\
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{reg.helper_arg_type()} {reg.helper_arg_name()} = 0;
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"""))
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## Print useful information about HVX registers
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for regtype, regid in regs:
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if hex_common.is_written(regid):
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numresults += 1
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if hex_common.is_scalar_reg(regtype):
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numscalarresults += 1
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if hex_common.is_readwrite(regid):
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if hex_common.is_scalar_reg(regtype):
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numscalarreadwrite += 1
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reg = hex_common.get_register(tag, regtype, regid)
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if reg.is_hvx_reg():
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reg.helper_hvx_desc(f)
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if numscalarresults > 1:
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## The helper is bogus when there is more than one result
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f.write(
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f"void HELPER({tag})(CPUHexagonState *env) " f"{{ BOGUS_HELPER({tag}); }}\n"
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)
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else:
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## The return type of the function is the type of the destination
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## register (if scalar)
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i = 0
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for regtype, regid in regs:
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if hex_common.is_written(regid):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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continue
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else:
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gen_helper_return_type_pair(f, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_hvx_reg(regtype):
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continue
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else:
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gen_helper_return_type(f, regtype, regid, i)
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else:
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hex_common.bad_register(regtype, regid)
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i += 1
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if hex_common.need_slot(tag):
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if "A_LOAD" in hex_common.attribdict[tag]:
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f.write(hex_common.code_fmt(f"""\
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bool pkt_has_store_s1 = slotval & 0x1;
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"""))
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f.write(hex_common.code_fmt(f"""\
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uint32_t slot = slotval >> 1;
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"""))
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if numscalarresults == 0:
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f.write("void")
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f.write(f" HELPER({tag})(CPUHexagonState *env")
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if "A_FPOP" in hex_common.attribdict[tag]:
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f.write(hex_common.code_fmt(f"""\
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arch_fpop_start(env);
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"""))
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## Arguments include the vector destination operands
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i = 1
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for regtype, regid in regs:
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if hex_common.is_written(regid):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_arg_ext_pair(f, regtype, regid, i)
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else:
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continue
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elif hex_common.is_single(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_arg_ext(f, regtype, regid, i)
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else:
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# This is the return value of the function
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continue
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else:
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hex_common.bad_register(regtype, regid)
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i += 1
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f.write(hex_common.code_fmt(f"""\
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{hex_common.semdict[tag]}
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"""))
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## For conditional instructions, we pass in the destination register
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if "A_CONDEXEC" in hex_common.attribdict[tag]:
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for regtype, regid in regs:
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if hex_common.is_writeonly(regid) and not hex_common.is_hvx_reg(
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regtype
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):
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gen_helper_arg_opn(f, regtype, regid, i, tag)
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i += 1
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if "A_FPOP" in hex_common.attribdict[tag]:
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f.write(hex_common.code_fmt(f"""\
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arch_fpop_end(env);
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"""))
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## Arguments to the helper function are the source regs and immediates
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for regtype, regid in regs:
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if hex_common.is_read(regid):
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if hex_common.is_hvx_reg(regtype) and hex_common.is_readwrite(regid):
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continue
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gen_helper_arg_opn(f, regtype, regid, i, tag)
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i += 1
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for immlett, bits, immshift in imms:
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gen_helper_arg_imm(f, immlett)
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i += 1
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## Return the scalar result
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for regtype, regid in regs:
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reg = hex_common.get_register(tag, regtype, regid)
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if reg.is_written() and not reg.is_hvx_reg():
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f.write(hex_common.code_fmt(f"""\
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return {reg.helper_arg_name()};
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"""))
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if hex_common.need_pkt_has_multi_cof(tag):
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f.write(", uint32_t pkt_has_multi_cof")
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if (hex_common.need_pkt_need_commit(tag)):
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f.write(", uint32_t pkt_need_commit")
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if hex_common.need_PC(tag):
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if i > 0:
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f.write(", ")
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f.write("target_ulong PC")
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i += 1
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if hex_common.helper_needs_next_PC(tag):
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if i > 0:
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f.write(", ")
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f.write("target_ulong next_PC")
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i += 1
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if hex_common.need_slot(tag):
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if i > 0:
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f.write(", ")
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f.write("uint32_t slotval")
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i += 1
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if hex_common.need_part1(tag):
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if i > 0:
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f.write(", ")
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f.write("uint32_t part1")
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f.write(")\n{\n")
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if hex_common.need_ea(tag):
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gen_decl_ea(f)
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## Declare the return variable
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i = 0
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if "A_CONDEXEC" not in hex_common.attribdict[tag]:
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for regtype, regid in regs:
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if hex_common.is_writeonly(regid):
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gen_helper_dest_decl_opn(f, regtype, regid, i)
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i += 1
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for regtype, regid in regs:
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if hex_common.is_read(regid):
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if hex_common.is_pair(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_src_var_ext_pair(f, regtype, regid, i)
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elif hex_common.is_single(regid):
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if hex_common.is_hvx_reg(regtype):
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gen_helper_src_var_ext(f, regtype, regid)
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else:
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hex_common.bad_register(regtype, regid)
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if hex_common.need_slot(tag):
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if "A_LOAD" in hex_common.attribdict[tag]:
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f.write(" bool pkt_has_store_s1 = slotval & 0x1;\n")
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f.write(" uint32_t slot = slotval >> 1;\n")
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if "A_FPOP" in hex_common.attribdict[tag]:
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f.write(" arch_fpop_start(env);\n")
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f.write(f" {hex_common.semdict[tag]}\n")
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if "A_FPOP" in hex_common.attribdict[tag]:
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f.write(" arch_fpop_end(env);\n")
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## Save/return the return variable
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for regtype, regid in regs:
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if hex_common.is_written(regid):
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gen_helper_return_opn(f, regtype, regid, i)
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f.write("}\n\n")
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## End of the helper definition
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f.write("}\n\n")
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## End of the helper definition
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def main():
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@ -370,6 +119,7 @@ def main():
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if is_idef_parser_enabled:
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hex_common.read_idef_parser_enabled_file(sys.argv[5])
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hex_common.calculate_attribs()
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hex_common.init_registers()
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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@ -275,10 +275,6 @@ def need_PC(tag):
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return "A_IMPLICIT_READS_PC" in attribdict[tag]
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def helper_needs_next_PC(tag):
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return "A_CALL" in attribdict[tag]
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def need_next_PC(tag):
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return "A_CALL" in attribdict[tag]
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@ -680,6 +676,10 @@ class VRegDest(Register, Hvx, Dest):
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"""))
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def log_write(self, f, tag):
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pass
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def helper_hvx_desc(self, f):
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f.write(code_fmt(f"""\
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/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
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"""))
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class VRegSource(Register, Hvx, OldSource):
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def decl_tcg(self, f, tag, regno):
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@ -692,6 +692,10 @@ class VRegSource(Register, Hvx, OldSource):
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TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
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tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
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"""))
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def helper_hvx_desc(self, f):
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f.write(code_fmt(f"""\
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/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
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"""))
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class VRegNewSource(Register, Hvx, NewSource):
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def decl_tcg(self, f, tag, regno):
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@ -701,6 +705,10 @@ class VRegNewSource(Register, Hvx, NewSource):
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const intptr_t {self.hvx_off()} =
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||||
ctx_future_vreg_off(ctx, {self.reg_num}, 1, true);
|
||||
"""))
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class VRegReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -719,6 +727,10 @@ class VRegReadWrite(Register, Hvx, ReadWrite):
|
|||
"""))
|
||||
def log_write(self, f, tag):
|
||||
pass
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class VRegTmp(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -739,6 +751,10 @@ class VRegTmp(Register, Hvx, ReadWrite):
|
|||
gen_log_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},
|
||||
{hvx_newv(tag)});
|
||||
"""))
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class VRegPairDest(Register, Hvx, Dest):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -754,6 +770,10 @@ class VRegPairDest(Register, Hvx, Dest):
|
|||
"""))
|
||||
def log_write(self, f, tag):
|
||||
pass
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class VRegPairSource(Register, Hvx, OldSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -773,6 +793,10 @@ class VRegPairSource(Register, Hvx, OldSource):
|
|||
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
||||
"""))
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class VRegPairReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -797,6 +821,10 @@ class VRegPairReadWrite(Register, Hvx, ReadWrite):
|
|||
gen_log_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},
|
||||
{hvx_newv(tag)});
|
||||
"""))
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class QRegDest(Register, Hvx, Dest):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -812,6 +840,10 @@ class QRegDest(Register, Hvx, Dest):
|
|||
"""))
|
||||
def log_write(self, f, tag):
|
||||
pass
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class QRegSource(Register, Hvx, OldSource):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -825,6 +857,10 @@ class QRegSource(Register, Hvx, OldSource):
|
|||
TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});
|
||||
"""))
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
class QRegReadWrite(Register, Hvx, ReadWrite):
|
||||
def decl_tcg(self, f, tag, regno):
|
||||
|
|
@ -843,6 +879,10 @@ class QRegReadWrite(Register, Hvx, ReadWrite):
|
|||
"""))
|
||||
def log_write(self, f, tag):
|
||||
pass
|
||||
def helper_hvx_desc(self, f):
|
||||
f.write(code_fmt(f"""\
|
||||
/* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */
|
||||
"""))
|
||||
|
||||
def init_registers():
|
||||
regs = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue