mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: List unsupported shift-imm opcodes
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.orgmaster
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931c8cc270
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a566da1b02
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@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
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handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
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handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
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immh, immb, opcode, rn, rd);
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immh, immb, opcode, rn, rd);
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break;
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break;
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default:
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case 0x8: /* SRI */
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case 0xc: /* SQSHLU */
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case 0xe: /* SQSHL, UQSHL */
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case 0x1f: /* FCVTZS, FCVTZU */
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unsupported_encoding(s, insn);
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unsupported_encoding(s, insn);
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break;
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break;
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default:
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unallocated_encoding(s);
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break;
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}
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}
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}
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}
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@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
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handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
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handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
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opcode, rn, rd);
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opcode, rn, rd);
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break;
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break;
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case 0x8: /* SRI */
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case 0xc: /* SQSHLU */
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case 0xe: /* SQSHL, UQSHL */
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case 0x1f: /* FCVTZS/ FCVTZU */
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case 0x1f: /* FCVTZS/ FCVTZU */
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unsupported_encoding(s, insn);
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unsupported_encoding(s, insn);
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return;
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return;
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default:
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default:
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unsupported_encoding(s, insn);
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unallocated_encoding(s);
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return;
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return;
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}
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}
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}
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}
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