mirror of https://github.com/proxmox/mirror_qemu
tcg/s390: Use softmmu fast path for unaligned accesses
Signed-off-by: Richard Henderson <rth@twiddle.net>master
parent
68d45bb61c
commit
a5e39810b9
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@ -1504,20 +1504,36 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
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static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
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static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
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int mem_index, bool is_ld)
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int mem_index, bool is_ld)
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{
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{
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TCGMemOp s_bits = opc & MO_SIZE;
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int s_mask = (1 << (opc & MO_SIZE)) - 1;
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uint64_t tlb_mask = TARGET_PAGE_MASK | ((1 << s_bits) - 1);
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int ofs, a_off;
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int ofs;
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uint64_t tlb_mask;
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/* For aligned accesses, we check the first byte and include the alignment
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bits within the address. For unaligned access, we check that we don't
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cross pages using the address of the last byte of the access. */
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if ((opc & MO_AMASK) == MO_ALIGN || s_mask == 0) {
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a_off = 0;
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tlb_mask = TARGET_PAGE_MASK | s_mask;
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} else {
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a_off = s_mask;
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tlb_mask = TARGET_PAGE_MASK;
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}
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if (facilities & FACILITY_GEN_INST_EXT) {
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if (facilities & FACILITY_GEN_INST_EXT) {
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tcg_out_risbg(s, TCG_REG_R2, addr_reg,
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tcg_out_risbg(s, TCG_REG_R2, addr_reg,
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64 - CPU_TLB_BITS - CPU_TLB_ENTRY_BITS,
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64 - CPU_TLB_BITS - CPU_TLB_ENTRY_BITS,
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63 - CPU_TLB_ENTRY_BITS,
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63 - CPU_TLB_ENTRY_BITS,
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64 + CPU_TLB_ENTRY_BITS - TARGET_PAGE_BITS, 1);
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64 + CPU_TLB_ENTRY_BITS - TARGET_PAGE_BITS, 1);
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tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
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if (a_off) {
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tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
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tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
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} else {
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tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
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}
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} else {
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} else {
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tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
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tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_R3, addr_reg);
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tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
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tgen_andi(s, TCG_TYPE_I64, TCG_REG_R2,
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tgen_andi(s, TCG_TYPE_I64, TCG_REG_R2,
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(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
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tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
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tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
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