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ppc: Add POWER8 IAMR register 

With appropriate AMR-like masks. Not actually used by the translation
logic at that point

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR)
      changed gen_spr_amr() prototype ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
master
Benjamin Herrenschmidt 2016-03-21 13:52:38 +01:00 committed by David Gibson
parent 97eaf30ec6
commit a6eabb9e59
2 changed files with 40 additions and 2 deletions
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1
target-ppc/cpu.h
View File

@ -1360,6 +1360,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
#define SPR_BOOKE_CSRR0 (0x03A)
#define SPR_BOOKE_CSRR1 (0x03B)
#define SPR_BOOKE_DEAR (0x03D)
#define SPR_IAMR (0x03D)
#define SPR_BOOKE_ESR (0x03E)
#define SPR_BOOKE_IVPR (0x03F)
#define SPR_MPC_EIE (0x050)

41
target-ppc/translate_init.c
View File

@ -1126,9 +1126,39 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t1);
tcg_temp_free(t2);
}
static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
/* Note, the HV=1 case is handled earlier by simply using
* spr_write_generic for HV mode in the SPR table
*/
/* Build insertion mask into t1 based on context */
gen_load_spr(t1, SPR_AMOR);
/* Mask new bits into t2 */
tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
/* Load AMR and clear new bits in t0 */
gen_load_spr(t0, SPR_IAMR);
tcg_gen_andc_tl(t0, t0, t1);
/* Or'in new bits and write it out */
tcg_gen_or_tl(t0, t0, t2);
gen_store_spr(SPR_IAMR, t0);
spr_store_dump_spr(SPR_IAMR);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
#endif /* CONFIG_USER_ONLY */
static void gen_spr_amr (CPUPPCState *env)
static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
{
#ifndef CONFIG_USER_ONLY
/* Virtual Page Class Key protection */
@ -1154,6 +1184,13 @@ static void gen_spr_amr (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
if (has_iamr) {
spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_iamr,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_IAMR, 0);
}
#endif /* !CONFIG_USER_ONLY */
}
#endif /* TARGET_PPC64 */
@ -8000,7 +8037,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
case BOOK3S_CPU_POWER7:
case BOOK3S_CPU_POWER8:
gen_spr_book3s_ids(env);
gen_spr_amr(env);
gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
gen_spr_book3s_purr(env);
env->ci_large_pages = true;
break;