mirror of https://github.com/proxmox/mirror_qemu
aspeed/smc: Introduce a new addr_width() class handler
The AST2400 SPI controller has a transitional HW interface and it stores the address width currently in use in a different register than all the other SMC controllers. It needs special handling when working in 4B mode. Make it clear through a class handler. This also removes another use of the segments array. Signed-off-by: Cédric Le Goater <clg@kaod.org>master
parent
71255c48e7
commit
a779e37c68
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@ -196,7 +196,6 @@
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* controller. These can be changed when board is initialized with the
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* Segment Address Registers.
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*/
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static const AspeedSegments aspeed_2400_spi1_segments[];
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static const AspeedSegments aspeed_2500_spi1_segments[];
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static const AspeedSegments aspeed_2500_spi2_segments[];
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@ -382,15 +381,15 @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
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return cmd;
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}
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static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
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static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
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{
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const AspeedSMCState *s = fl->controller;
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AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
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if (asc->segments == aspeed_2400_spi1_segments) {
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return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE;
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if (asc->addr_width) {
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return asc->addr_width(s);
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} else {
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return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs));
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return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3;
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}
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}
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@ -450,7 +449,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
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{
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const AspeedSMCState *s = fl->controller;
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uint8_t cmd = aspeed_smc_flash_cmd(fl);
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int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
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int i = aspeed_smc_flash_addr_width(fl);
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/* Flash access can not exceed CS segment */
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addr = aspeed_smc_check_segment_addr(fl, addr);
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@ -558,7 +557,7 @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
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unsigned size)
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{
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AspeedSMCState *s = fl->controller;
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uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
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uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
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trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
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(uint8_t) data & 0xff);
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@ -1384,6 +1383,11 @@ static const AspeedSegments aspeed_2400_spi1_segments[] = {
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{ 0x30000000, 64 * MiB },
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};
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static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s)
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{
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return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3;
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}
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static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -1405,6 +1409,7 @@ static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
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asc->segment_to_reg = aspeed_smc_segment_to_reg;
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asc->reg_to_segment = aspeed_smc_reg_to_segment;
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asc->dma_ctrl = aspeed_smc_dma_ctrl;
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asc->addr_width = aspeed_2400_spi1_addr_width;
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}
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static const TypeInfo aspeed_2400_spi1_info = {
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@ -111,6 +111,7 @@ struct AspeedSMCClass {
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void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg,
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AspeedSegments *seg);
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void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
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int (*addr_width)(const AspeedSMCState *s);
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};
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#endif /* ASPEED_SMC_H */
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