mirror of https://github.com/proxmox/mirror_qemu
target-ppc: Convert ppc cpu savevm to VMStateDescription
The savevm code for the powerpc cpu emulation is currently based around the old register_savevm() rather than register_vmstate() method. It's also rather broken, missing some important state on some CPU models. This patch completely rewrites the savevm for target-ppc, using the new VMStateDescription approach. Exactly what needs to be saved in what configurations has been more carefully examined, too. This introduces a new version (5) of the cpu save format. The old load function is retained to support version 4 images. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-2-git-send-email-aliguori@us.ibm.com [aik: ppc cpu savevm convertion fixed to use PowerPCCPU instead of CPUPPCState] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>master
Alexey Kardashevskiy
Anthony Liguori
parent
fdc43322c9
commit
a90db1584a
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@ -109,4 +109,8 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_ppc_cpu;
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#endif
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#endif
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@ -948,7 +948,7 @@ struct CPUPPCState {
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#if defined(TARGET_PPC64)
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/* PowerPC 64 SLB area */
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ppc_slb_t slb[64];
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int slb_nr;
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int32_t slb_nr;
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#endif
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/* segment registers */
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hwaddr htab_base;
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@ -957,11 +957,11 @@ struct CPUPPCState {
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/* externally stored hash table */
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uint8_t *external_htab;
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/* BATs */
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int nb_BATs;
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uint32_t nb_BATs;
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target_ulong DBAT[2][8];
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target_ulong IBAT[2][8];
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/* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
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int nb_tlb; /* Total number of TLB */
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int32_t nb_tlb; /* Total number of TLB */
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int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
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int nb_ways; /* Number of ways in the TLB set */
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int last_way; /* Last used way used to allocate TLB in a LRU way */
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@ -1176,8 +1176,6 @@ static inline CPUPPCState *cpu_init(const char *cpu_model)
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#define cpu_signal_handler cpu_ppc_signal_handler
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#define cpu_list ppc_cpu_list
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#define CPU_SAVE_VERSION 4
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
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@ -1,96 +1,12 @@
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "helper_regs.h"
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void cpu_save(QEMUFile *f, void *opaque)
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static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
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{
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CPUPPCState *env = (CPUPPCState *)opaque;
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unsigned int i, j;
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uint32_t fpscr;
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target_ulong xer;
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for (i = 0; i < 32; i++)
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qemu_put_betls(f, &env->gpr[i]);
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#if !defined(TARGET_PPC64)
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for (i = 0; i < 32; i++)
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qemu_put_betls(f, &env->gprh[i]);
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#endif
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qemu_put_betls(f, &env->lr);
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qemu_put_betls(f, &env->ctr);
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for (i = 0; i < 8; i++)
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qemu_put_be32s(f, &env->crf[i]);
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xer = cpu_read_xer(env);
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qemu_put_betls(f, &xer);
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qemu_put_betls(f, &env->reserve_addr);
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qemu_put_betls(f, &env->msr);
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for (i = 0; i < 4; i++)
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qemu_put_betls(f, &env->tgpr[i]);
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for (i = 0; i < 32; i++) {
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union {
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float64 d;
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uint64_t l;
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} u;
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u.d = env->fpr[i];
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qemu_put_be64(f, u.l);
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}
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fpscr = env->fpscr;
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qemu_put_be32s(f, &fpscr);
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qemu_put_sbe32s(f, &env->access_type);
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#if defined(TARGET_PPC64)
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qemu_put_betls(f, &env->spr[SPR_ASR]);
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qemu_put_sbe32s(f, &env->slb_nr);
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#endif
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qemu_put_betls(f, &env->spr[SPR_SDR1]);
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for (i = 0; i < 32; i++)
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qemu_put_betls(f, &env->sr[i]);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 8; j++)
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qemu_put_betls(f, &env->DBAT[i][j]);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 8; j++)
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qemu_put_betls(f, &env->IBAT[i][j]);
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qemu_put_sbe32s(f, &env->nb_tlb);
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qemu_put_sbe32s(f, &env->tlb_per_way);
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qemu_put_sbe32s(f, &env->nb_ways);
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qemu_put_sbe32s(f, &env->last_way);
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qemu_put_sbe32s(f, &env->id_tlbs);
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qemu_put_sbe32s(f, &env->nb_pids);
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if (env->tlb.tlb6) {
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// XXX assumes 6xx
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for (i = 0; i < env->nb_tlb; i++) {
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qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
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qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
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qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
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}
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}
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for (i = 0; i < 4; i++)
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qemu_put_betls(f, &env->pb[i]);
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for (i = 0; i < 1024; i++)
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qemu_put_betls(f, &env->spr[i]);
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qemu_put_be32s(f, &env->vscr);
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qemu_put_be64s(f, &env->spe_acc);
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qemu_put_be32s(f, &env->spe_fscr);
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qemu_put_betls(f, &env->msr_mask);
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qemu_put_be32s(f, &env->flags);
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qemu_put_sbe32s(f, &env->error_code);
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qemu_put_be32s(f, &env->pending_interrupts);
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qemu_put_be32s(f, &env->irq_input_state);
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for (i = 0; i < POWERPC_EXCP_NB; i++)
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qemu_put_betls(f, &env->excp_vectors[i]);
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qemu_put_betls(f, &env->excp_prefix);
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qemu_put_betls(f, &env->ivor_mask);
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qemu_put_betls(f, &env->ivpr_mask);
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qemu_put_betls(f, &env->hreset_vector);
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qemu_put_betls(f, &env->nip);
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qemu_put_betls(f, &env->hflags);
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qemu_put_betls(f, &env->hflags_nmsr);
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qemu_put_sbe32s(f, &env->mmu_idx);
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qemu_put_sbe32(f, 0);
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}
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int cpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUPPCState *env = (CPUPPCState *)opaque;
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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unsigned int i, j;
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target_ulong sdr1;
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uint32_t fpscr;
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@ -177,3 +93,442 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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static int get_avr(QEMUFile *f, void *pv, size_t size)
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{
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ppc_avr_t *v = pv;
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v->u64[0] = qemu_get_be64(f);
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v->u64[1] = qemu_get_be64(f);
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return 0;
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}
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static void put_avr(QEMUFile *f, void *pv, size_t size)
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{
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ppc_avr_t *v = pv;
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qemu_put_be64(f, v->u64[0]);
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qemu_put_be64(f, v->u64[1]);
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}
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const VMStateInfo vmstate_info_avr = {
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.name = "avr",
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.get = get_avr,
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.put = put_avr,
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};
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#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
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#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
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VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
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static void cpu_pre_save(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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int i;
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env->spr[SPR_LR] = env->lr;
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env->spr[SPR_CTR] = env->ctr;
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env->spr[SPR_XER] = env->xer;
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#if defined(TARGET_PPC64)
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env->spr[SPR_CFAR] = env->cfar;
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#endif
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env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
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for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
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env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
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env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
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env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
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env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
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}
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for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
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env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
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env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
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env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
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env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
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}
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}
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static int cpu_post_load(void *opaque, int version_id)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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int i;
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env->lr = env->spr[SPR_LR];
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env->ctr = env->spr[SPR_CTR];
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env->xer = env->spr[SPR_XER];
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#if defined(TARGET_PPC64)
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env->cfar = env->spr[SPR_CFAR];
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#endif
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env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
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for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
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env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
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env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
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env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
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env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
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}
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for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
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env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
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env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
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env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
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env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
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}
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/* Restore htab_base and htab_mask variables */
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ppc_store_sdr1(env, env->spr[SPR_SDR1]);
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hreg_compute_hflags(env);
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hreg_compute_mem_idx(env);
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return 0;
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}
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static bool fpu_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags & PPC_FLOAT);
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}
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static const VMStateDescription vmstate_fpu = {
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.name = "cpu/fpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
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VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool altivec_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags & PPC_ALTIVEC);
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}
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static const VMStateDescription vmstate_altivec = {
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.name = "cpu/altivec",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
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VMSTATE_UINT32(env.vscr, PowerPCCPU),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool vsx_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags2 & PPC2_VSX);
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}
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static const VMStateDescription vmstate_vsx = {
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.name = "cpu/vsx",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool sr_needed(void *opaque)
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{
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#ifdef TARGET_PPC64
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PowerPCCPU *cpu = opaque;
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return !(cpu->env.mmu_model & POWERPC_MMU_64);
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#else
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return true;
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#endif
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}
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static const VMStateDescription vmstate_sr = {
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.name = "cpu/sr",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
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VMSTATE_END_OF_LIST()
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},
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};
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#ifdef TARGET_PPC64
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static int get_slbe(QEMUFile *f, void *pv, size_t size)
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{
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ppc_slb_t *v = pv;
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v->esid = qemu_get_be64(f);
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v->vsid = qemu_get_be64(f);
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return 0;
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}
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static void put_slbe(QEMUFile *f, void *pv, size_t size)
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{
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ppc_slb_t *v = pv;
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qemu_put_be64(f, v->esid);
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qemu_put_be64(f, v->vsid);
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}
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const VMStateInfo vmstate_info_slbe = {
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.name = "slbe",
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.get = get_slbe,
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.put = put_slbe,
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};
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#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
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#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
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VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
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static bool slb_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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/* We don't support any of the old segment table based 64-bit CPUs */
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return (cpu->env.mmu_model & POWERPC_MMU_64);
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}
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static const VMStateDescription vmstate_slb = {
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.name = "cpu/slb",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
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VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, 64),
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VMSTATE_END_OF_LIST()
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}
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};
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#endif /* TARGET_PPC64 */
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static const VMStateDescription vmstate_tlb6xx_entry = {
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.name = "cpu/tlb6xx_entry",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
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VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
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VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool tlb6xx_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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return env->nb_tlb && (env->tlb_type == TLB_6XX);
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}
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static const VMStateDescription vmstate_tlb6xx = {
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.name = "cpu/tlb6xx",
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.version_id = 1,
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.minimum_version_id = 1,
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||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
||||
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
|
||||
env.nb_tlb,
|
||||
vmstate_tlb6xx_entry,
|
||||
ppc6xx_tlb_t),
|
||||
VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_tlbemb_entry = {
|
||||
.name = "cpu/tlbemb_entry",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_UINT64(RPN, ppcemb_tlb_t),
|
||||
VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
|
||||
VMSTATE_UINTTL(PID, ppcemb_tlb_t),
|
||||
VMSTATE_UINTTL(size, ppcemb_tlb_t),
|
||||
VMSTATE_UINT32(prot, ppcemb_tlb_t),
|
||||
VMSTATE_UINT32(attr, ppcemb_tlb_t),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
||||
static bool tlbemb_needed(void *opaque)
|
||||
{
|
||||
PowerPCCPU *cpu = opaque;
|
||||
CPUPPCState *env = &cpu->env;
|
||||
|
||||
return env->nb_tlb && (env->tlb_type == TLB_EMB);
|
||||
}
|
||||
|
||||
static bool pbr403_needed(void *opaque)
|
||||
{
|
||||
PowerPCCPU *cpu = opaque;
|
||||
uint32_t pvr = cpu->env.spr[SPR_PVR];
|
||||
|
||||
return (pvr & 0xffff0000) == 0x00200000;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_pbr403 = {
|
||||
.name = "cpu/pbr403",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_tlbemb = {
|
||||
.name = "cpu/tlb6xx",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
||||
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
|
||||
env.nb_tlb,
|
||||
vmstate_tlbemb_entry,
|
||||
ppcemb_tlb_t),
|
||||
/* 403 protection registers */
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
.subsections = (VMStateSubsection []) {
|
||||
{
|
||||
.vmsd = &vmstate_pbr403,
|
||||
.needed = pbr403_needed,
|
||||
} , {
|
||||
/* empty */
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_tlbmas_entry = {
|
||||
.name = "cpu/tlbmas_entry",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_UINT32(mas8, ppcmas_tlb_t),
|
||||
VMSTATE_UINT32(mas1, ppcmas_tlb_t),
|
||||
VMSTATE_UINT64(mas2, ppcmas_tlb_t),
|
||||
VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
};
|
||||
|
||||
static bool tlbmas_needed(void *opaque)
|
||||
{
|
||||
PowerPCCPU *cpu = opaque;
|
||||
CPUPPCState *env = &cpu->env;
|
||||
|
||||
return env->nb_tlb && (env->tlb_type == TLB_MAS);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_tlbmas = {
|
||||
.name = "cpu/tlbmas",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField []) {
|
||||
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
||||
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
|
||||
env.nb_tlb,
|
||||
vmstate_tlbmas_entry,
|
||||
ppcmas_tlb_t),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
const VMStateDescription vmstate_ppc_cpu = {
|
||||
.name = "cpu",
|
||||
.version_id = 5,
|
||||
.minimum_version_id = 5,
|
||||
.minimum_version_id_old = 4,
|
||||
.load_state_old = cpu_load_old,
|
||||
.pre_save = cpu_pre_save,
|
||||
.post_load = cpu_post_load,
|
||||
.fields = (VMStateField []) {
|
||||
/* Verify we haven't changed the pvr */
|
||||
VMSTATE_UINTTL_EQUAL(env.spr[SPR_PVR], PowerPCCPU),
|
||||
|
||||
/* User mode architected state */
|
||||
VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
|
||||
#if !defined(TARGET_PPC64)
|
||||
VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
|
||||
#endif
|
||||
VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
|
||||
VMSTATE_UINTTL(env.nip, PowerPCCPU),
|
||||
|
||||
/* SPRs */
|
||||
VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
|
||||
VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
|
||||
|
||||
/* Reservation */
|
||||
VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
|
||||
|
||||
/* Supervisor mode architected state */
|
||||
VMSTATE_UINTTL(env.msr, PowerPCCPU),
|
||||
|
||||
/* Internal state */
|
||||
VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
|
||||
/* FIXME: access_type? */
|
||||
|
||||
/* Sanity checking */
|
||||
VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
|
||||
VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
|
||||
VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
|
||||
VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
|
||||
VMSTATE_END_OF_LIST()
|
||||
},
|
||||
.subsections = (VMStateSubsection []) {
|
||||
{
|
||||
.vmsd = &vmstate_fpu,
|
||||
.needed = fpu_needed,
|
||||
} , {
|
||||
.vmsd = &vmstate_altivec,
|
||||
.needed = altivec_needed,
|
||||
} , {
|
||||
.vmsd = &vmstate_vsx,
|
||||
.needed = vsx_needed,
|
||||
} , {
|
||||
.vmsd = &vmstate_sr,
|
||||
.needed = sr_needed,
|
||||
} , {
|
||||
#ifdef TARGET_PPC64
|
||||
.vmsd = &vmstate_slb,
|
||||
.needed = slb_needed,
|
||||
} , {
|
||||
#endif /* TARGET_PPC64 */
|
||||
.vmsd = &vmstate_tlb6xx,
|
||||
.needed = tlb6xx_needed,
|
||||
} , {
|
||||
.vmsd = &vmstate_tlbemb,
|
||||
.needed = tlbemb_needed,
|
||||
} , {
|
||||
.vmsd = &vmstate_tlbmas,
|
||||
.needed = tlbmas_needed,
|
||||
} , {
|
||||
/* empty */
|
||||
}
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8462,6 +8462,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
|
|||
cc->gdb_write_register = ppc_cpu_gdb_write_register;
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
|
||||
cc->vmsd = &vmstate_ppc_cpu;
|
||||
#endif
|
||||
|
||||
cc->gdb_num_core_regs = 71;
|
||||
|
|
|
|||
Loading…
Reference in New Issue