From aa6e4986b8f6c435bf4e8aa4328b06d9e84524bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Canet?= Date: Thu, 24 Nov 2011 14:31:13 +0100 Subject: [PATCH] mcf_uart: convert to memory API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Benoît Canet Signed-off-by: Avi Kivity --- hw/mcf.h | 11 +++++++---- hw/mcf5206.c | 25 +++++++++++++------------ hw/mcf5208.c | 6 +++--- hw/mcf_uart.c | 34 +++++++++++++++------------------- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/hw/mcf.h b/hw/mcf.h index 572424d09c..e2f6727c57 100644 --- a/hw/mcf.h +++ b/hw/mcf.h @@ -5,11 +5,14 @@ struct MemoryRegion; /* mcf_uart.c */ -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr); -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); +uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr, + unsigned size); +void mcf_uart_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size); void *mcf_uart_init(qemu_irq irq, CharDriverState *chr); -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, - CharDriverState *chr); +void mcf_uart_mm_init(struct MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, CharDriverState *chr); /* mcf_intc.c */ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); diff --git a/hw/mcf5206.c b/hw/mcf5206.c index 987687d3f9..7b6d501447 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -263,16 +263,17 @@ static void m5206_mbar_reset(m5206_mbar_state *s) s->par = 0; } -static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset) +static uint64_t m5206_mbar_read(m5206_mbar_state *s, + uint64_t offset, unsigned size) { if (offset >= 0x100 && offset < 0x120) { return m5206_timer_read(s->timer[0], offset - 0x100); } else if (offset >= 0x120 && offset < 0x140) { return m5206_timer_read(s->timer[1], offset - 0x120); } else if (offset >= 0x140 && offset < 0x160) { - return mcf_uart_read(s->uart[0], offset - 0x140); + return mcf_uart_read(s->uart[0], offset - 0x140, size); } else if (offset >= 0x180 && offset < 0x1a0) { - return mcf_uart_read(s->uart[1], offset - 0x180); + return mcf_uart_read(s->uart[1], offset - 0x180, size); } switch (offset) { case 0x03: return s->scr; @@ -301,7 +302,7 @@ static uint32_t m5206_mbar_read(m5206_mbar_state *s, uint32_t offset) } static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, - uint32_t value) + uint64_t value, unsigned size) { if (offset >= 0x100 && offset < 0x120) { m5206_timer_write(s->timer[0], offset - 0x100, value); @@ -310,10 +311,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, m5206_timer_write(s->timer[1], offset - 0x120, value); return; } else if (offset >= 0x140 && offset < 0x160) { - mcf_uart_write(s->uart[0], offset - 0x140, value); + mcf_uart_write(s->uart[0], offset - 0x140, value, size); return; } else if (offset >= 0x180 && offset < 0x1a0) { - mcf_uart_write(s->uart[1], offset - 0x180, value); + mcf_uart_write(s->uart[1], offset - 0x180, value, size); return; } switch (offset) { @@ -387,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset) } return val & 0xff; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 1); } static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) @@ -411,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset) val |= m5206_mbar_readb(opaque, offset + 1); return val; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 2); } static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) @@ -429,7 +430,7 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset) val |= m5206_mbar_readw(opaque, offset + 2); return val; } - return m5206_mbar_read(s, offset); + return m5206_mbar_read(s, offset, 4); } static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, @@ -458,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset, m5206_mbar_writew(opaque, offset & ~1, tmp); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 1); } static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, @@ -486,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset, m5206_mbar_writeb(opaque, offset + 1, value & 0xff); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 2); } static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, @@ -504,7 +505,7 @@ static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset, m5206_mbar_writew(opaque, offset + 2, value & 0xffff); return; } - m5206_mbar_write(s, offset, value); + m5206_mbar_write(s, offset, value, 4); } static const MemoryRegionOps m5206_mbar_ops = { diff --git a/hw/mcf5208.c b/hw/mcf5208.c index 1c2c0c48aa..0119430b29 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -223,9 +223,9 @@ static void mcf5208evb_init(ram_addr_t ram_size, /* Internal peripherals. */ pic = mcf_intc_init(0xfc048000, env); - mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); - mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); - mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); + mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]); + mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]); + mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]); mcf5208_sys_init(address_space_mem, pic); diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c index e6b2ab067a..ec6a87f238 100644 --- a/hw/mcf_uart.c +++ b/hw/mcf_uart.c @@ -8,8 +8,10 @@ #include "hw.h" #include "mcf.h" #include "qemu-char.h" +#include "exec-memory.h" typedef struct { + MemoryRegion iomem; uint8_t mr[2]; uint8_t sr; uint8_t isr; @@ -64,7 +66,8 @@ static void mcf_uart_update(mcf_uart_state *s) qemu_set_irq(s->irq, (s->isr & s->imr) != 0); } -uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr) +uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr, + unsigned size) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -182,7 +185,8 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd) } } -void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val) +void mcf_uart_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { mcf_uart_state *s = (mcf_uart_state *)opaque; switch (addr & 0x3f) { @@ -283,28 +287,20 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr) return s; } - -static CPUReadMemoryFunc * const mcf_uart_readfn[] = { - mcf_uart_read, - mcf_uart_read, - mcf_uart_read +static const MemoryRegionOps mcf_uart_ops = { + .read = mcf_uart_read, + .write = mcf_uart_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const mcf_uart_writefn[] = { - mcf_uart_write, - mcf_uart_write, - mcf_uart_write -}; - -void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, +void mcf_uart_mm_init(MemoryRegion *sysmem, + target_phys_addr_t base, + qemu_irq irq, CharDriverState *chr) { mcf_uart_state *s; - int iomemtype; s = mcf_uart_init(irq, chr); - iomemtype = cpu_register_io_memory(mcf_uart_readfn, - mcf_uart_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x40, iomemtype); + memory_region_init_io(&s->iomem, &mcf_uart_ops, s, "uart", 0x40); + memory_region_add_subregion(sysmem, base, &s->iomem); }