mirror of https://github.com/proxmox/mirror_qemu
target-m68k: Implement bitfield ops for registers
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>master
Richard Henderson
Laurent Vivier
parent
b6af8ea602
commit
ac815f46a3
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@ -3504,6 +3504,210 @@ DISAS_INSN(rotate_mem)
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set_cc_op(s, CC_OP_FLAGS);
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}
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DISAS_INSN(bfext_reg)
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{
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int ext = read_im16(env, s);
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int is_sign = insn & 0x200;
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TCGv src = DREG(insn, 0);
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TCGv dst = DREG(ext, 12);
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int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
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int ofs = extract32(ext, 6, 5); /* big bit-endian */
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int pos = 32 - ofs - len; /* little bit-endian */
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TCGv tmp = tcg_temp_new();
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TCGv shift;
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/* In general, we're going to rotate the field so that it's at the
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top of the word and then right-shift by the compliment of the
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width to extend the field. */
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if (ext & 0x20) {
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/* Variable width. */
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if (ext & 0x800) {
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/* Variable offset. */
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tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
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tcg_gen_rotl_i32(tmp, src, tmp);
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} else {
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tcg_gen_rotli_i32(tmp, src, ofs);
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}
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shift = tcg_temp_new();
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tcg_gen_neg_i32(shift, DREG(ext, 0));
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tcg_gen_andi_i32(shift, shift, 31);
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tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
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if (is_sign) {
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tcg_gen_mov_i32(dst, QREG_CC_N);
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} else {
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tcg_gen_shr_i32(dst, tmp, shift);
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}
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tcg_temp_free(shift);
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} else {
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/* Immediate width. */
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if (ext & 0x800) {
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/* Variable offset */
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tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
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tcg_gen_rotl_i32(tmp, src, tmp);
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src = tmp;
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pos = 32 - len;
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} else {
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/* Immediate offset. If the field doesn't wrap around the
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end of the word, rely on (s)extract completely. */
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if (pos < 0) {
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tcg_gen_rotli_i32(tmp, src, ofs);
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src = tmp;
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pos = 32 - len;
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}
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}
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tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
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if (is_sign) {
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tcg_gen_mov_i32(dst, QREG_CC_N);
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} else {
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tcg_gen_extract_i32(dst, src, pos, len);
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}
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}
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tcg_temp_free(tmp);
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set_cc_op(s, CC_OP_LOGIC);
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}
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DISAS_INSN(bfop_reg)
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{
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int ext = read_im16(env, s);
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TCGv src = DREG(insn, 0);
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int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
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int ofs = extract32(ext, 6, 5); /* big bit-endian */
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TCGv mask;
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if ((ext & 0x820) == 0) {
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/* Immediate width and offset. */
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uint32_t maski = 0x7fffffffu >> (len - 1);
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if (ofs + len <= 32) {
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tcg_gen_shli_i32(QREG_CC_N, src, ofs);
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} else {
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tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
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}
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tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
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mask = tcg_const_i32(ror32(maski, ofs));
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} else {
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TCGv tmp = tcg_temp_new();
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if (ext & 0x20) {
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/* Variable width */
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tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
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tcg_gen_andi_i32(tmp, tmp, 31);
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mask = tcg_const_i32(0x7fffffffu);
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tcg_gen_shr_i32(mask, mask, tmp);
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} else {
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/* Immediate width */
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mask = tcg_const_i32(0x7fffffffu >> (len - 1));
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}
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if (ext & 0x800) {
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/* Variable offset */
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tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
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tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
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tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
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tcg_gen_rotr_i32(mask, mask, tmp);
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} else {
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/* Immediate offset (and variable width) */
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tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
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tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
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tcg_gen_rotri_i32(mask, mask, ofs);
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}
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tcg_temp_free(tmp);
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}
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set_cc_op(s, CC_OP_LOGIC);
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switch (insn & 0x0f00) {
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case 0x0a00: /* bfchg */
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tcg_gen_eqv_i32(src, src, mask);
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break;
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case 0x0c00: /* bfclr */
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tcg_gen_and_i32(src, src, mask);
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break;
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case 0x0e00: /* bfset */
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tcg_gen_orc_i32(src, src, mask);
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break;
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case 0x0800: /* bftst */
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/* flags already set; no other work to do. */
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break;
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default:
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g_assert_not_reached();
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}
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tcg_temp_free(mask);
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}
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DISAS_INSN(bfins_reg)
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{
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int ext = read_im16(env, s);
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TCGv dst = DREG(insn, 0);
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TCGv src = DREG(ext, 12);
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int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
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int ofs = extract32(ext, 6, 5); /* big bit-endian */
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int pos = 32 - ofs - len; /* little bit-endian */
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TCGv tmp;
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tmp = tcg_temp_new();
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if (ext & 0x20) {
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/* Variable width */
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tcg_gen_neg_i32(tmp, DREG(ext, 0));
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tcg_gen_andi_i32(tmp, tmp, 31);
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tcg_gen_shl_i32(QREG_CC_N, src, tmp);
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} else {
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/* Immediate width */
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tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
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}
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set_cc_op(s, CC_OP_LOGIC);
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/* Immediate width and offset */
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if ((ext & 0x820) == 0) {
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/* Check for suitability for deposit. */
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if (pos >= 0) {
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tcg_gen_deposit_i32(dst, dst, src, pos, len);
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} else {
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uint32_t maski = -2U << (len - 1);
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uint32_t roti = (ofs + len) & 31;
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tcg_gen_andi_i32(tmp, src, ~maski);
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tcg_gen_rotri_i32(tmp, tmp, roti);
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tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
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tcg_gen_or_i32(dst, dst, tmp);
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}
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} else {
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TCGv mask = tcg_temp_new();
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TCGv rot = tcg_temp_new();
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if (ext & 0x20) {
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/* Variable width */
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tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
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tcg_gen_andi_i32(rot, rot, 31);
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tcg_gen_movi_i32(mask, -2);
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tcg_gen_shl_i32(mask, mask, rot);
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tcg_gen_mov_i32(rot, DREG(ext, 0));
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tcg_gen_andc_i32(tmp, src, mask);
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} else {
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/* Immediate width (variable offset) */
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uint32_t maski = -2U << (len - 1);
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tcg_gen_andi_i32(tmp, src, ~maski);
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tcg_gen_movi_i32(mask, maski);
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tcg_gen_movi_i32(rot, len & 31);
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}
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if (ext & 0x800) {
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/* Variable offset */
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tcg_gen_add_i32(rot, rot, DREG(ext, 6));
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} else {
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/* Immediate offset (variable width) */
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tcg_gen_addi_i32(rot, rot, ofs);
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}
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tcg_gen_andi_i32(rot, rot, 31);
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tcg_gen_rotr_i32(mask, mask, rot);
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tcg_gen_rotr_i32(tmp, tmp, rot);
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tcg_gen_and_i32(dst, dst, mask);
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tcg_gen_or_i32(dst, dst, tmp);
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tcg_temp_free(rot);
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tcg_temp_free(mask);
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}
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tcg_temp_free(tmp);
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}
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DISAS_INSN(ff1)
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{
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TCGv reg;
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@ -4595,6 +4799,12 @@ void register_m68k_insns (CPUM68KState *env)
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INSN(rotate8_reg, e030, f0f0, M68000);
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INSN(rotate16_reg, e070, f0f0, M68000);
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INSN(rotate_mem, e4c0, fcc0, M68000);
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INSN(bfext_reg, e9c0, fdf8, BITFIELD); /* bfextu & bfexts */
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INSN(bfins_reg, efc0, fff8, BITFIELD);
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INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
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INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
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INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
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INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
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INSN(undef_fpu, f000, f000, CF_ISA_A);
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INSN(fpu, f200, ffc0, CF_FPU);
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INSN(fbcc, f280, ffc0, CF_FPU);
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