sifive: Move QOM typedefs and add missing includes

Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.

Patch generated using:

 $ ./scripts/codeconverter/converter.py -i \
   --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')

which will split "typdef struct { ... } TypedefName"
declarations.

Followed by:

 $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
    $(git grep -l '' -- '*.[ch]')

which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

hw/intc/sifive_plic.h

@@ -22,9 +22,11 @@
 #define HW_SIFIVE_PLIC_H
 
 #include "hw/sysbus.h"
+#include "qom/object.h"
 
 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
 
+typedef struct SiFivePLICState SiFivePLICState;
 #define SIFIVE_PLIC(obj) \
     OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC)
 
@@ -41,7 +43,7 @@ typedef struct PLICAddr {
     PLICMode mode;
 } PLICAddr;
 
-typedef struct SiFivePLICState {
+struct SiFivePLICState {
     /*< private >*/
     SysBusDevice parent_obj;
 
@@ -69,7 +71,7 @@ typedef struct SiFivePLICState {
     uint32_t context_base;
     uint32_t context_stride;
     uint32_t aperture_size;
-} SiFivePLICState;
+};
 
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
     uint32_t hartid_base, uint32_t num_sources,

include/hw/char/sifive_uart.h

@@ -22,6 +22,7 @@
 
 #include "chardev/char-fe.h"
 #include "hw/sysbus.h"
+#include "qom/object.h"
 
 enum {
     SIFIVE_UART_TXFIFO        = 0,
@@ -51,10 +52,11 @@ enum {
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
 
+typedef struct SiFiveUARTState SiFiveUARTState;
 #define SIFIVE_UART(obj) \
     OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
 
-typedef struct SiFiveUARTState {
+struct SiFiveUARTState {
     /*< private >*/
     SysBusDevice parent_obj;
 
@@ -69,7 +71,7 @@ typedef struct SiFiveUARTState {
     uint32_t txctrl;
     uint32_t rxctrl;
     uint32_t div;
-} SiFiveUARTState;
+};
 
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     Chardev *chr, qemu_irq irq);

include/hw/gpio/sifive_gpio.h

@@ -15,8 +15,10 @@
 #define SIFIVE_GPIO_H
 
 #include "hw/sysbus.h"
+#include "qom/object.h"
 
 #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
+typedef struct SIFIVEGPIOState SIFIVEGPIOState;
 #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
 
 #define SIFIVE_GPIO_PINS 32
@@ -41,7 +43,7 @@
 #define SIFIVE_GPIO_REG_IOF_SEL    0x03C
 #define SIFIVE_GPIO_REG_OUT_XOR    0x040
 
-typedef struct SIFIVEGPIOState {
+struct SIFIVEGPIOState {
     SysBusDevice parent_obj;
 
     MemoryRegion mmio;
@@ -71,6 +73,6 @@ typedef struct SIFIVEGPIOState {
 
     /* config */
     uint32_t ngpio;
-} SIFIVEGPIOState;
+};
 
 #endif /* SIFIVE_GPIO_H */

include/hw/misc/sifive_e_prci.h

@@ -18,6 +18,7 @@
 
 #ifndef HW_SIFIVE_E_PRCI_H
 #define HW_SIFIVE_E_PRCI_H
+#include "qom/object.h"
 
 enum {
     SIFIVE_E_PRCI_HFROSCCFG = 0x0,
@@ -51,10 +52,11 @@ enum {
 
 #define TYPE_SIFIVE_E_PRCI      "riscv.sifive.e.prci"
 
+typedef struct SiFiveEPRCIState SiFiveEPRCIState;
 #define SIFIVE_E_PRCI(obj) \
     OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
 
-typedef struct SiFiveEPRCIState {
+struct SiFiveEPRCIState {
     /*< private >*/
     SysBusDevice parent_obj;
 
@@ -64,7 +66,7 @@ typedef struct SiFiveEPRCIState {
     uint32_t hfxosccfg;
     uint32_t pllcfg;
     uint32_t plloutdiv;
-} SiFiveEPRCIState;
+};
 
 DeviceState *sifive_e_prci_create(hwaddr addr);
 

include/hw/misc/sifive_test.h

@@ -20,19 +20,21 @@
 #define HW_SIFIVE_TEST_H
 
 #include "hw/sysbus.h"
+#include "qom/object.h"
 
 #define TYPE_SIFIVE_TEST "riscv.sifive.test"
 
+typedef struct SiFiveTestState SiFiveTestState;
 #define SIFIVE_TEST(obj) \
     OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
 
-typedef struct SiFiveTestState {
+struct SiFiveTestState {
     /*< private >*/
     SysBusDevice parent_obj;
 
     /*< public >*/
     MemoryRegion mmio;
-} SiFiveTestState;
+};
 
 enum {
     FINISHER_FAIL = 0x3333,

include/hw/misc/sifive_u_otp.h

@@ -18,6 +18,7 @@
 
 #ifndef HW_SIFIVE_U_OTP_H
 #define HW_SIFIVE_U_OTP_H
+#include "qom/object.h"
 
 #define SIFIVE_U_OTP_PA         0x00
 #define SIFIVE_U_OTP_PAIO       0x04
@@ -49,10 +50,11 @@
 
 #define TYPE_SIFIVE_U_OTP           "riscv.sifive.u.otp"
 
+typedef struct SiFiveUOTPState SiFiveUOTPState;
 #define SIFIVE_U_OTP(obj) \
     OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
 
-typedef struct SiFiveUOTPState {
+struct SiFiveUOTPState {
     /*< private >*/
     SysBusDevice parent_obj;
 
@@ -75,6 +77,6 @@ typedef struct SiFiveUOTPState {
     uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
     /* config */
     uint32_t serial;
-} SiFiveUOTPState;
+};
 
 #endif /* HW_SIFIVE_U_OTP_H */

include/hw/misc/sifive_u_prci.h

@@ -18,6 +18,7 @@
 
 #ifndef HW_SIFIVE_U_PRCI_H
 #define HW_SIFIVE_U_PRCI_H
+#include "qom/object.h"
 
 #define SIFIVE_U_PRCI_HFXOSCCFG     0x00
 #define SIFIVE_U_PRCI_COREPLLCFG0   0x04
@@ -58,10 +59,11 @@
 
 #define TYPE_SIFIVE_U_PRCI      "riscv.sifive.u.prci"
 
+typedef struct SiFiveUPRCIState SiFiveUPRCIState;
 #define SIFIVE_U_PRCI(obj) \
     OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
 
-typedef struct SiFiveUPRCIState {
+struct SiFiveUPRCIState {
     /*< private >*/
     SysBusDevice parent_obj;
 
@@ -76,7 +78,7 @@ typedef struct SiFiveUPRCIState {
     uint32_t coreclksel;
     uint32_t devicesreset;
     uint32_t clkmuxstatus;
-} SiFiveUPRCIState;
+};
 
 /*
  * Clock indexes for use by Device Tree data and the PRCI driver.