mirror of https://github.com/proxmox/mirror_qemu
tcg/ppc: Support TCG_COND_TST{EQ,NE}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
Richard Henderson
parent
282ef7e8ef
commit
ad788aebba
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@ -283,11 +283,15 @@ static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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return false;
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}
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static bool mask_operand(uint32_t c, int *mb, int *me);
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static bool mask64_operand(uint64_t c, int *mb, int *me);
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/* test if a constant matches the constraint */
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static bool tcg_target_const_match(int64_t sval, int ct,
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TCGType type, TCGCond cond, int vece)
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{
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uint64_t uval = sval;
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int mb, me;
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if (ct & TCG_CT_CONST) {
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return 1;
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@ -316,6 +320,17 @@ static bool tcg_target_const_match(int64_t sval, int ct,
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case TCG_COND_GTU:
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ct |= TCG_CT_CONST_U16;
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break;
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case TCG_COND_TSTEQ:
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case TCG_COND_TSTNE:
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if ((uval & ~0xffff) == 0 || (uval & ~0xffff0000ull) == 0) {
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return 1;
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}
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if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32
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? mask_operand(uval, &mb, &me)
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: mask64_operand(uval << clz64(uval), &mb, &me)) {
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return 1;
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}
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return 0;
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default:
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g_assert_not_reached();
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}
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@ -703,9 +718,11 @@ enum {
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CR_SO
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};
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static const uint32_t tcg_to_bc[] = {
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static const uint32_t tcg_to_bc[16] = {
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[TCG_COND_EQ] = BC | BI(0, CR_EQ) | BO_COND_TRUE,
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[TCG_COND_NE] = BC | BI(0, CR_EQ) | BO_COND_FALSE,
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[TCG_COND_TSTEQ] = BC | BI(0, CR_EQ) | BO_COND_TRUE,
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[TCG_COND_TSTNE] = BC | BI(0, CR_EQ) | BO_COND_FALSE,
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[TCG_COND_LT] = BC | BI(0, CR_LT) | BO_COND_TRUE,
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[TCG_COND_GE] = BC | BI(0, CR_LT) | BO_COND_FALSE,
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[TCG_COND_LE] = BC | BI(0, CR_GT) | BO_COND_FALSE,
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@ -717,9 +734,11 @@ static const uint32_t tcg_to_bc[] = {
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};
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/* The low bit here is set if the RA and RB fields must be inverted. */
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static const uint32_t tcg_to_isel[] = {
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static const uint32_t tcg_to_isel[16] = {
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[TCG_COND_EQ] = ISEL | BC_(0, CR_EQ),
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[TCG_COND_NE] = ISEL | BC_(0, CR_EQ) | 1,
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[TCG_COND_TSTEQ] = ISEL | BC_(0, CR_EQ),
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[TCG_COND_TSTNE] = ISEL | BC_(0, CR_EQ) | 1,
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[TCG_COND_LT] = ISEL | BC_(0, CR_LT),
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[TCG_COND_GE] = ISEL | BC_(0, CR_LT) | 1,
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[TCG_COND_LE] = ISEL | BC_(0, CR_GT) | 1,
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@ -872,19 +891,31 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
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return true;
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}
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static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb)
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static void tcg_out_rld_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb, bool rc)
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{
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
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sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
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mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
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tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
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tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc);
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}
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static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb, int me)
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static void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb)
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{
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tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
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tcg_out_rld_rc(s, op, ra, rs, sh, mb, false);
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}
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static void tcg_out_rlw_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb, int me, bool rc)
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{
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tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me) | rc);
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}
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static void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
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int sh, int mb, int me)
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{
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tcg_out_rlw_rc(s, op, ra, rs, sh, mb, me, false);
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}
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static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
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@ -1702,6 +1733,50 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
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return false;
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}
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/*
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* Set dest non-zero if and only if (arg1 & arg2) is non-zero.
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* If RC, then also set RC0.
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*/
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static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2,
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bool const_arg2, TCGType type, bool rc)
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{
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int mb, me;
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if (!const_arg2) {
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tcg_out32(s, AND | SAB(arg1, dest, arg2) | rc);
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return;
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}
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if (type == TCG_TYPE_I32) {
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arg2 = (uint32_t)arg2;
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} else if (arg2 == (uint32_t)arg2) {
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type = TCG_TYPE_I32;
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}
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if ((arg2 & ~0xffff) == 0) {
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tcg_out32(s, ANDI | SAI(arg1, dest, arg2));
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return;
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}
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if ((arg2 & ~0xffff0000ull) == 0) {
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tcg_out32(s, ANDIS | SAI(arg1, dest, arg2 >> 16));
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return;
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}
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if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
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if (mask_operand(arg2, &mb, &me)) {
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tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc);
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return;
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}
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} else {
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int sh = clz64(arg2);
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if (mask64_operand(arg2 << sh, &mb, &me)) {
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tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc);
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return;
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}
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}
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/* Constraints should satisfy this. */
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g_assert_not_reached();
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}
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static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
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int const_arg2, int cr, TCGType type)
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{
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@ -1736,6 +1811,12 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
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imm = 0;
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break;
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case TCG_COND_TSTEQ:
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case TCG_COND_TSTNE:
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tcg_debug_assert(cr == 0);
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tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, true);
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return;
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case TCG_COND_LT:
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case TCG_COND_GE:
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case TCG_COND_LE:
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@ -1946,6 +2027,16 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
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tcg_out_setcond_ne0(s, type, arg0, arg1, neg);
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break;
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case TCG_COND_TSTEQ:
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tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, false);
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tcg_out_setcond_eq0(s, type, arg0, TCG_REG_R0, neg);
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break;
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case TCG_COND_TSTNE:
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tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, false);
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tcg_out_setcond_ne0(s, type, arg0, TCG_REG_R0, neg);
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break;
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case TCG_COND_LE:
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case TCG_COND_LEU:
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inv = true;
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@ -2118,6 +2209,21 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
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tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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break;
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case TCG_COND_TSTEQ:
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case TCG_COND_TSTNE:
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if (blconst) {
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tcg_out_andi32(s, TCG_REG_R0, al, bl);
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} else {
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tcg_out32(s, AND | SAB(al, TCG_REG_R0, bl));
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}
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if (bhconst) {
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tcg_out_andi32(s, TCG_REG_TMP1, ah, bh);
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} else {
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tcg_out32(s, AND | SAB(ah, TCG_REG_TMP1, bh));
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}
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tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1);
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break;
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case TCG_COND_LT:
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case TCG_COND_LE:
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case TCG_COND_GT:
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@ -143,7 +143,7 @@ typedef enum {
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#define TCG_TARGET_HAS_qemu_ldst_i128 \
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(TCG_TARGET_REG_BITS == 64 && have_isa_2_07)
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#define TCG_TARGET_HAS_tst 0
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#define TCG_TARGET_HAS_tst 1
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/*
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* While technically Altivec could support V64, it has no 64-bit store
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