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target/mips: Convert MSA 2R instruction format to decodetree 

Convert 2-register operations to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-10-19 10:23:08 +02:00
parent 675bf34a6f
commit adcff99a6b
2 changed files with 19 additions and 75 deletions
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3
target/mips/tcg/msa.decode
View File

@ -84,6 +84,9 @@ BNZ 010001 111 .. ..... ................ @bz
SRLRI 011110 011 ....... ..... ..... 001010 @bit
FILL 011110 11000000 .. ..... ..... 011110 @2r
PCNT 011110 11000001 .. ..... ..... 011110 @2r
NLOC 011110 11000010 .. ..... ..... 011110 @2r
NLZC 011110 11000011 .. ..... ..... 011110 @2r
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf

91
target/mips/tcg/msa_translate.c
View File

@ -49,7 +49,7 @@ enum {
};
enum {
/* VEC/2R instruction */
/* VEC instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
@ -58,13 +58,6 @@ enum {
OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@ -300,6 +293,7 @@ static inline bool check_msa_enabled(DisasContext *ctx)
}
typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);
typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
@ -312,6 +306,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
#define TRANS_DF_iv(NAME, trans_func, gen_func) \
TRANS_DF_x(iv, NAME, trans_func, gen_func)
#define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func)
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@ -1835,75 +1832,22 @@ static void gen_msa_3rf(DisasContext *ctx)
tcg_temp_free_i32(twt);
}
static void gen_msa_2r(DisasContext *ctx)
static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
gen_helper_pii *gen_msa_2r)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x3;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
switch (MASK_MSA_2R(ctx->opcode)) {
case OPC_NLOC_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_nloc_b(cpu_env, twd, tws);
break;
case DF_HALF:
gen_helper_msa_nloc_h(cpu_env, twd, tws);
break;
case DF_WORD:
gen_helper_msa_nloc_w(cpu_env, twd, tws);
break;
case DF_DOUBLE:
gen_helper_msa_nloc_d(cpu_env, twd, tws);
break;
}
break;
case OPC_NLZC_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_nlzc_b(cpu_env, twd, tws);
break;
case DF_HALF:
gen_helper_msa_nlzc_h(cpu_env, twd, tws);
break;
case DF_WORD:
gen_helper_msa_nlzc_w(cpu_env, twd, tws);
break;
case DF_DOUBLE:
gen_helper_msa_nlzc_d(cpu_env, twd, tws);
break;
}
break;
case OPC_PCNT_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_pcnt_b(cpu_env, twd, tws);
break;
case DF_HALF:
gen_helper_msa_pcnt_h(cpu_env, twd, tws);
break;
case DF_WORD:
gen_helper_msa_pcnt_w(cpu_env, twd, tws);
break;
case DF_DOUBLE:
gen_helper_msa_pcnt_d(cpu_env, twd, tws);
break;
}
break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
break;
if (!check_msa_enabled(ctx)) {
return true;
}
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws));
return true;
}
TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc);
TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
{
if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
@ -2010,9 +1954,6 @@ static void gen_msa_vec(DisasContext *ctx)
case OPC_BSEL_V:
gen_msa_vec_v(ctx);
break;
case OPC_MSA_2R:
gen_msa_2r(ctx);
break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);