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target/mips: Inline gen_helper_0e0i() 

gen_helper_0e0i() is one-line long and is only used twice:
simply inline it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-08-15 15:48:58 +02:00
parent a1b4b060d7
commit ae71abadd5
1 changed files with 2 additions and 6 deletions
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8
target/mips/tcg/translate.c
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@ -1213,10 +1213,6 @@ TCGv_i64 fpu_f64[32];
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
gen_helper_##name(cpu_env, tcg_constant_i32(arg)); \
} while (0)
#define gen_helper_0e1i(name, arg1, arg2) do { \
gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \
} while (0)
@ -1378,7 +1374,7 @@ void generate_exception_err(DisasContext *ctx, int excp, int err)
void generate_exception(DisasContext *ctx, int excp)
{
gen_helper_0e0i(raise_exception, excp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
}
void generate_exception_end(DisasContext *ctx, int excp)
@ -14188,7 +14184,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
MIPS_INVAL("PMON / selsl");
gen_reserved_instruction(ctx);
#else
gen_helper_0e0i(pmon, sa);
gen_helper_pmon(cpu_env, tcg_constant_i32(sa));
#endif
break;
case OPC_SYSCALL: