From 52f5903a27f3bf862aced027dfce4444eed4e2fe Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:45 +0200 Subject: [PATCH 01/12] move MemMapEntry It is defined twice already. Move to a common header file to remove duplication and make it available to everybody. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-2-kraxel@redhat.com --- hw/arm/sbsa-ref.c | 5 ----- include/exec/hwaddr.h | 5 +++++ include/hw/arm/virt.h | 5 ----- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 257ada9425..9c3a893bed 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -80,11 +80,6 @@ enum { SBSA_EHCI, }; -typedef struct MemMapEntry { - hwaddr base; - hwaddr size; -} MemMapEntry; - struct SBSAMachineState { MachineState parent; struct arm_boot_info bootinfo; diff --git a/include/exec/hwaddr.h b/include/exec/hwaddr.h index a71c93cc81..8f16d179a8 100644 --- a/include/exec/hwaddr.h +++ b/include/exec/hwaddr.h @@ -18,4 +18,9 @@ typedef uint64_t hwaddr; #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 +typedef struct MemMapEntry { + hwaddr base; + hwaddr size; +} MemMapEntry; + #endif diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index d018a4f297..655b895d5e 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -111,11 +111,6 @@ typedef enum VirtGICType { VIRT_GIC_VERSION_NOSEL, } VirtGICType; -typedef struct MemMapEntry { - hwaddr base; - hwaddr size; -} MemMapEntry; - struct VirtMachineClass { MachineClass parent; bool disallow_affinity_adjustment; From 5b85eabe68f9e75d85e0c0db3b9eade75e7217f0 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:46 +0200 Subject: [PATCH 02/12] acpi: add acpi_dsdt_add_gpex Add helper function to generate dsdt aml code for the gpex pci host. Largely copied from arm/virt. Configuration is handled by passing a config struct instead of looked up from memory map. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-3-kraxel@redhat.com --- hw/pci-host/gpex-acpi.c | 179 +++++++++++++++++++++++++++++++++++++ hw/pci-host/meson.build | 1 + include/hw/pci-host/gpex.h | 11 +++ 3 files changed, 191 insertions(+) create mode 100644 hw/pci-host/gpex-acpi.c diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c new file mode 100644 index 0000000000..6fb951a0c1 --- /dev/null +++ b/hw/pci-host/gpex-acpi.c @@ -0,0 +1,179 @@ +#include "qemu/osdep.h" +#include "hw/acpi/aml-build.h" +#include "hw/pci-host/gpex.h" + +void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) +{ + int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; + Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; + int i, slot_no; + + Aml *dev = aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + /* Declare the PCI Routing Table. */ + Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); + for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { + for (i = 0; i < PCI_NUM_PINS; i++) { + int gsi = (i + slot_no) % PCI_NUM_PINS; + Aml *pkg = aml_package(4); + aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); + aml_append(pkg, aml_int(i)); + aml_append(pkg, aml_name("GSI%d", gsi)); + aml_append(pkg, aml_int(0)); + aml_append(rt_pkg, pkg); + } + } + aml_append(dev, aml_name_decl("_PRT", rt_pkg)); + + /* Create GSI link device */ + for (i = 0; i < PCI_NUM_PINS; i++) { + uint32_t irqs = cfg->irq + i; + Aml *dev_gsi = aml_device("GSI%d", i); + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); + crs = aml_resource_template(); + aml_append(crs, + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_EXCLUSIVE, &irqs, 1)); + aml_append(dev_gsi, aml_name_decl("_PRS", crs)); + crs = aml_resource_template(); + aml_append(crs, + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_EXCLUSIVE, &irqs, 1)); + aml_append(dev_gsi, aml_name_decl("_CRS", crs)); + method = aml_method("_SRS", 1, AML_NOTSERIALIZED); + aml_append(dev_gsi, method); + aml_append(dev, dev_gsi); + } + + method = aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(cfg->ecam.base))); + aml_append(dev, method); + + method = aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf = aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + if (cfg->mmio32.size) { + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + cfg->mmio32.base, + cfg->mmio32.base + cfg->mmio32.size - 1, + 0x0000, + cfg->mmio32.size)); + } + if (cfg->pio.size) { + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, + cfg->pio.size - 1, + cfg->pio.base, + cfg->pio.size)); + } + if (cfg->mmio64.size) { + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + cfg->mmio64.base, + cfg->mmio64.base + cfg->mmio64.size - 1, + 0x0000, + cfg->mmio64.size)); + } + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + /* Declare an _OSC (OS Control Handoff) method */ + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + method = aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, + aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); + + /* PCI Firmware Specification 3.0 + * 4.5.1. _OSC Interface for PCI Host Bridge Devices + * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is + * identified by the Universal Unique IDentifier (UUID) + * 33DB4D5B-1FF7-401C-9657-7441C03DD766 + */ + UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); + ifctx = aml_if(aml_equal(aml_arg(0), UUID)); + aml_append(ifctx, + aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); + aml_append(ifctx, + aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); + aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); + aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); + + /* + * Allow OS control for all 5 features: + * PCIeHotplug SHPCHotplug PME AER PCIeCapability. + */ + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), + aml_name("CTRL"))); + + ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), + aml_name("CDW1"))); + aml_append(ifctx, ifctx1); + + ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); + aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), + aml_name("CDW1"))); + aml_append(ifctx, ifctx1); + + aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); + aml_append(ifctx, aml_return(aml_arg(3))); + aml_append(method, ifctx); + + elsectx = aml_else(); + aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), + aml_name("CDW1"))); + aml_append(elsectx, aml_return(aml_arg(3))); + aml_append(method, elsectx); + aml_append(dev, method); + + method = aml_method("_DSM", 4, AML_NOTSERIALIZED); + + /* PCI Firmware Specification 3.0 + * 4.6.1. _DSM for PCI Express Slot Information + * The UUID in _DSM in this context is + * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} + */ + UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); + ifctx = aml_if(aml_equal(aml_arg(0), UUID)); + ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); + uint8_t byte_list[1] = {1}; + buf = aml_buffer(1, byte_list); + aml_append(ifctx1, aml_return(buf)); + aml_append(ifctx, ifctx1); + aml_append(method, ifctx); + + byte_list[0] = 0; + buf = aml_buffer(1, byte_list); + aml_append(method, aml_return(buf)); + aml_append(dev, method); + + Aml *dev_res0 = aml_device("%s", "RES0"); + aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); + crs = aml_resource_template(); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + cfg->ecam.base, + cfg->ecam.base + cfg->ecam.size - 1, + 0x0000, + cfg->ecam.size)); + aml_append(dev_res0, aml_name_decl("_CRS", crs)); + aml_append(dev, dev_res0); + aml_append(scope, dev); +} diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index cd52f6ff1c..e6d1b89684 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -3,6 +3,7 @@ pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c')) pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c')) +pci_ss.add(when: 'CONFIG_ACPI', if_true: files('gpex-acpi.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_Q35', if_true: files('q35.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_XILINX', if_true: files('xilinx-pcie.c')) pci_ss.add(when: 'CONFIG_PCI_I440FX', if_true: files('i440fx.c')) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 7abdb8b406..d52ea80d4e 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -20,6 +20,7 @@ #ifndef HW_GPEX_H #define HW_GPEX_H +#include "exec/hwaddr.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" #include "hw/pci/pcie_host.h" @@ -52,6 +53,16 @@ struct GPEXHost { int irq_num[GPEX_NUM_IRQS]; }; +struct GPEXConfig { + MemMapEntry ecam; + MemMapEntry mmio32; + MemMapEntry mmio64; + MemMapEntry pio; + int irq; +}; + int gpex_set_irq_num(GPEXHost *s, int index, int gsi); +void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); + #endif /* HW_GPEX_H */ From 06d2dd4911a9d2b7c8ac20f834cfdc2a950a13c2 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:47 +0200 Subject: [PATCH 03/12] arm: use acpi_dsdt_add_gpex Fill gpex config struct from memory map, then call the new acpi_dsdt_add_gpex helper function. No functional change. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-4-kraxel@redhat.com --- hw/arm/virt-acpi-build.c | 175 ++------------------------------------- 1 file changed, 9 insertions(+), 166 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6bff5e3738..9747a6458f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -44,6 +44,7 @@ #include "hw/acpi/tpm.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" #include "hw/arm/virt.h" #include "hw/mem/nvdimm.h" #include "hw/platform-bus.h" @@ -155,176 +156,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irq, bool use_highmem, bool highmem_ecam) { int ecam_id = VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; - int i, slot_no; - hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; - hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio = memmap[VIRT_PCIE_PIO].size; - hwaddr base_ecam = memmap[ecam_id].base; - hwaddr size_ecam = memmap[ecam_id].size; - int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; - - Aml *dev = aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - - /* Declare the PCI Routing Table. */ - Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); - for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { - for (i = 0; i < PCI_NUM_PINS; i++) { - int gsi = (i + slot_no) % PCI_NUM_PINS; - Aml *pkg = aml_package(4); - aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); - aml_append(pkg, aml_int(i)); - aml_append(pkg, aml_name("GSI%d", gsi)); - aml_append(pkg, aml_int(0)); - aml_append(rt_pkg, pkg); - } - } - aml_append(dev, aml_name_decl("_PRT", rt_pkg)); - - /* Create GSI link device */ - for (i = 0; i < PCI_NUM_PINS; i++) { - uint32_t irqs = irq + i; - Aml *dev_gsi = aml_device("GSI%d", i); - aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); - aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); - crs = aml_resource_template(); - aml_append(crs, - aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, - AML_EXCLUSIVE, &irqs, 1)); - aml_append(dev_gsi, aml_name_decl("_PRS", crs)); - crs = aml_resource_template(); - aml_append(crs, - aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, - AML_EXCLUSIVE, &irqs, 1)); - aml_append(dev_gsi, aml_name_decl("_CRS", crs)); - method = aml_method("_SRS", 1, AML_NOTSERIALIZED); - aml_append(dev_gsi, method); - aml_append(dev, dev_gsi); - } - - method = aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(base_ecam))); - aml_append(dev, method); - - method = aml_method("_CRS", 0, AML_NOTSERIALIZED); - Aml *rbuf = aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio, - size_pio)); + struct GPEXConfig cfg = { + .mmio32 = memmap[VIRT_PCIE_MMIO], + .pio = memmap[VIRT_PCIE_PIO], + .ecam = memmap[ecam_id], + .irq = irq, + }; if (use_highmem) { - hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; - - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); + cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; } - aml_append(method, aml_return(rbuf)); - aml_append(dev, method); - - /* Declare an _OSC (OS Control Handoff) method */ - aml_append(dev, aml_name_decl("SUPP", aml_int(0))); - aml_append(dev, aml_name_decl("CTRL", aml_int(0))); - method = aml_method("_OSC", 4, AML_NOTSERIALIZED); - aml_append(method, - aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); - - /* PCI Firmware Specification 3.0 - * 4.5.1. _OSC Interface for PCI Host Bridge Devices - * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is - * identified by the Universal Unique IDentifier (UUID) - * 33DB4D5B-1FF7-401C-9657-7441C03DD766 - */ - UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); - ifctx = aml_if(aml_equal(aml_arg(0), UUID)); - aml_append(ifctx, - aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); - aml_append(ifctx, - aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); - aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); - aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - - /* - * Allow OS control for all 5 features: - * PCIeHotplug SHPCHotplug PME AER PCIeCapability. - */ - aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), - aml_name("CTRL"))); - - ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); - aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), - aml_name("CDW1"))); - aml_append(ifctx, ifctx1); - - ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); - aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), - aml_name("CDW1"))); - aml_append(ifctx, ifctx1); - - aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); - aml_append(ifctx, aml_return(aml_arg(3))); - aml_append(method, ifctx); - - elsectx = aml_else(); - aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), - aml_name("CDW1"))); - aml_append(elsectx, aml_return(aml_arg(3))); - aml_append(method, elsectx); - aml_append(dev, method); - - method = aml_method("_DSM", 4, AML_NOTSERIALIZED); - - /* PCI Firmware Specification 3.0 - * 4.6.1. _DSM for PCI Express Slot Information - * The UUID in _DSM in this context is - * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} - */ - UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); - ifctx = aml_if(aml_equal(aml_arg(0), UUID)); - ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); - uint8_t byte_list[1] = {1}; - buf = aml_buffer(1, byte_list); - aml_append(ifctx1, aml_return(buf)); - aml_append(ifctx, ifctx1); - aml_append(method, ifctx); - - byte_list[0] = 0; - buf = aml_buffer(1, byte_list); - aml_append(method, aml_return(buf)); - aml_append(dev, method); - - Aml *dev_res0 = aml_device("%s", "RES0"); - aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); - crs = aml_resource_template(); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam, - base_ecam + size_ecam - 1, 0x0000, size_ecam)); - aml_append(dev_res0, aml_name_decl("_CRS", crs)); - aml_append(dev, dev_res0); - aml_append(scope, dev); + acpi_dsdt_add_gpex(scope, &cfg); } static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, From ebf187757048e972eea1054cb1b5b54a3e47356b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:48 +0200 Subject: [PATCH 04/12] microvm: add irq table Add a comment with a table listing the IRQs, both legacy pc and microvm side-by-side. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-5-kraxel@redhat.com --- include/hw/i386/microvm.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 3b9fd4ff17..0d61697c97 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -27,6 +27,28 @@ #include "hw/acpi/acpi_dev_interface.h" #include "qom/object.h" +/* + * IRQ | pc | microvm (acpi=on) + * --------+------------+------------------ + * 0 | pit | + * 1 | kbd | + * 2 | cascade | + * 3 | serial 1 | + * 4 | serial 0 | serial + * 5 | - | + * 6 | floppy | + * 7 | parallel | + * 8 | rtc | rtc (rtc=on) + * 9 | acpi | acpi (ged) + * 10 | pci lnk | + * 11 | pci lnk | + * 12 | ps2 | + * 13 | fpu | + * 14 | ide 0 | + * 15 | ide 1 | + * 16-23 | pci gsi | virtio + */ + /* Platform virtio definitions */ #define VIRTIO_MMIO_BASE 0xfeb00000 #define VIRTIO_NUM_TRANSPORTS 8 From 24db877ab6e6dc999016f1f29e59c7eb1539f5d3 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:49 +0200 Subject: [PATCH 05/12] microvm: add pcie support Uses the existing gpex device which is also used as pcie host bridge on arm/aarch64. For now only a 32bit mmio window and no ioport support. It is disabled by default, use "-machine microvm,pcie=on" to enable. ACPI support must be enabled too because the bus is declared in the DSDT table. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-6-kraxel@redhat.com --- hw/i386/Kconfig | 1 + hw/i386/acpi-microvm.c | 12 ++++++ hw/i386/microvm.c | 84 +++++++++++++++++++++++++++++++++++++++ include/hw/i386/microvm.h | 18 +++++++-- 4 files changed, 111 insertions(+), 4 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d0bd8b537d..32aa15533b 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -104,6 +104,7 @@ config MICROVM select MC146818RTC select VIRTIO_MMIO select ACPI_HW_REDUCED + select PCI_EXPRESS_GENERIC_BRIDGE config X86_IOMMU bool diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index df39c5d3bd..f16f231195 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -33,6 +33,8 @@ #include "hw/boards.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/microvm.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" #include "hw/virtio/virtio-mmio.h" #include "acpi-common.h" @@ -87,6 +89,15 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } +static void acpi_dsdt_add_pci(Aml *scope, MicrovmMachineState *mms) +{ + if (mms->pcie != ON_OFF_AUTO_ON) { + return; + } + + acpi_dsdt_add_gpex(scope, &mms->gpex); +} + static void build_dsdt_microvm(GArray *table_data, BIOSLinker *linker, MicrovmMachineState *mms) @@ -112,6 +123,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *linker, GED_MMIO_IRQ, AML_SYSTEM_MEMORY, GED_MMIO_BASE); acpi_dsdt_add_power_button(sb_scope); acpi_dsdt_add_virtio(sb_scope, mms); + acpi_dsdt_add_pci(sb_scope, mms); aml_append(dsdt, sb_scope); /* ACPI 5.0: Table 7-209 System State Package */ diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 60d3272230..273abe28c9 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -46,6 +46,7 @@ #include "hw/virtio/virtio-mmio.h" #include "hw/acpi/acpi.h" #include "hw/acpi/generic_event_device.h" +#include "hw/pci-host/gpex.h" #include "cpu.h" #include "elf.h" @@ -101,6 +102,55 @@ static void microvm_gsi_handler(void *opaque, int n, int level) qemu_set_irq(s->ioapic_irq[n], level); } +static void create_gpex(MicrovmMachineState *mms) +{ + X86MachineState *x86ms = X86_MACHINE(mms); + MemoryRegion *mmio32_alias; + MemoryRegion *mmio64_alias; + MemoryRegion *mmio_reg; + MemoryRegion *ecam_alias; + MemoryRegion *ecam_reg; + DeviceState *dev; + int i; + + dev = qdev_new(TYPE_GPEX_HOST); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + /* Map only the first size_ecam bytes of ECAM space */ + ecam_alias = g_new0(MemoryRegion, 1); + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, mms->gpex.ecam.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.ecam.base, ecam_alias); + + /* Map the MMIO window into system address space so as to expose + * the section of PCI MMIO space which starts at the same base address + * (ie 1:1 mapping for that part of PCI MMIO space visible through + * the window). + */ + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + if (mms->gpex.mmio32.size) { + mmio32_alias = g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg, + mms->gpex.mmio32.base, mms->gpex.mmio32.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.mmio32.base, mmio32_alias); + } + if (mms->gpex.mmio64.size) { + mmio64_alias = g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg, + mms->gpex.mmio64.base, mms->gpex.mmio64.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.mmio64.base, mmio64_alias); + } + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + x86ms->gsi[mms->gpex.irq + i]); + } +} + static void microvm_devices_init(MicrovmMachineState *mms) { X86MachineState *x86ms = X86_MACHINE(mms); @@ -147,6 +197,15 @@ static void microvm_devices_init(MicrovmMachineState *mms) x86ms->acpi_dev = HOTPLUG_HANDLER(dev); } + if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) { + mms->gpex.mmio32.base = PCIE_MMIO_BASE; + mms->gpex.mmio32.size = PCIE_MMIO_SIZE; + mms->gpex.ecam.base = PCIE_ECAM_BASE; + mms->gpex.ecam.size = PCIE_ECAM_SIZE; + mms->gpex.irq = PCIE_IRQ_BASE; + create_gpex(mms); + } + if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) { qemu_irq *i8259; @@ -446,6 +505,23 @@ static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name, visit_type_OnOffAuto(v, name, &mms->rtc, errp); } +static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + OnOffAuto pcie = mms->pcie; + + visit_type_OnOffAuto(v, name, &pcie, errp); +} + +static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &mms->pcie, errp); +} + static bool microvm_machine_get_isa_serial(Object *obj, Error **errp) { MicrovmMachineState *mms = MICROVM_MACHINE(obj); @@ -521,6 +597,7 @@ static void microvm_machine_initfn(Object *obj) mms->pic = ON_OFF_AUTO_AUTO; mms->pit = ON_OFF_AUTO_AUTO; mms->rtc = ON_OFF_AUTO_AUTO; + mms->pcie = ON_OFF_AUTO_AUTO; mms->isa_serial = true; mms->option_roms = true; mms->auto_kernel_cmdline = true; @@ -587,6 +664,13 @@ static void microvm_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, MICROVM_MACHINE_RTC, "Enable MC146818 RTC"); + object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto", + microvm_machine_get_pcie, + microvm_machine_set_pcie, + NULL, NULL); + object_class_property_set_description(oc, MICROVM_MACHINE_PCIE, + "Enable PCIe"); + object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL, microvm_machine_get_isa_serial, microvm_machine_set_isa_serial); diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 0d61697c97..91b064575d 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/i386/x86.h" #include "hw/acpi/acpi_dev_interface.h" +#include "hw/pci-host/gpex.h" #include "qom/object.h" /* @@ -42,10 +43,10 @@ * 9 | acpi | acpi (ged) * 10 | pci lnk | * 11 | pci lnk | - * 12 | ps2 | - * 13 | fpu | - * 14 | ide 0 | - * 15 | ide 1 | + * 12 | ps2 | pcie + * 13 | fpu | pcie + * 14 | ide 0 | pcie + * 15 | ide 1 | pcie * 16-23 | pci gsi | virtio */ @@ -59,10 +60,17 @@ #define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200) #define GED_MMIO_IRQ 9 +#define PCIE_MMIO_BASE 0xc0000000 +#define PCIE_MMIO_SIZE 0x20000000 +#define PCIE_ECAM_BASE 0xe0000000 +#define PCIE_ECAM_SIZE 0x10000000 +#define PCIE_IRQ_BASE 12 + /* Machine type options */ #define MICROVM_MACHINE_PIT "pit" #define MICROVM_MACHINE_PIC "pic" #define MICROVM_MACHINE_RTC "rtc" +#define MICROVM_MACHINE_PCIE "pcie" #define MICROVM_MACHINE_ISA_SERIAL "isa-serial" #define MICROVM_MACHINE_OPTION_ROMS "x-option-roms" #define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline" @@ -80,6 +88,7 @@ struct MicrovmMachineState { OnOffAuto pic; OnOffAuto pit; OnOffAuto rtc; + OnOffAuto pcie; bool isa_serial; bool option_roms; bool auto_kernel_cmdline; @@ -89,6 +98,7 @@ struct MicrovmMachineState { bool kernel_cmdline_fixed; Notifier machine_done; Notifier powerdown_req; + struct GPEXConfig gpex; }; #define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") From 8c2d9f9a38aa3237e16722e36e5a6b53a43fc7db Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:50 +0200 Subject: [PATCH 06/12] microvm/pcie: add 64bit mmio window Place the 64bit window at the top of the physical address space, assign 25% of the avaiable address space. Force cpu.host-phys-bits=on for microvm machine typs so this actually works reliable. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-7-kraxel@redhat.com --- hw/i386/microvm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 273abe28c9..17e3f2f152 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -198,6 +198,12 @@ static void microvm_devices_init(MicrovmMachineState *mms) } if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) { + /* use topmost 25% of the address space available */ + hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits; + if (phys_size > 0x1000000ll) { + mms->gpex.mmio64.size = phys_size / 4; + mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size; + } mms->gpex.mmio32.base = PCIE_MMIO_BASE; mms->gpex.mmio32.size = PCIE_MMIO_SIZE; mms->gpex.ecam.base = PCIE_ECAM_BASE; @@ -383,6 +389,9 @@ static void microvm_fix_kernel_cmdline(MachineState *machine) static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + X86CPU *cpu = X86_CPU(dev); + + cpu->host_phys_bits = true; /* need reliable phys-bits */ x86_cpu_pre_plug(hotplug_dev, dev, errp); } From 928dda43017681555a4f63196435881dbf7459ca Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:51 +0200 Subject: [PATCH 07/12] tests/acpi: allow updates for expected data files Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-8-kraxel@redhat.com --- tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..53109c22a5 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,6 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/microvm/DSDT.pcie32", +"tests/data/acpi/microvm/DSDT.pcie64", +"tests/data/acpi/virt/DSDT", +"tests/data/acpi/virt/DSDT.numamem", +"tests/data/acpi/virt/DSDT.memhp", From fe1e5cc805586d1f3e558e2a46f952d6e46c5cb0 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:52 +0200 Subject: [PATCH 08/12] tests/acpi: add empty tests/data/acpi/microvm/DSDT.pcie file Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-9-kraxel@redhat.com --- tests/data/acpi/microvm/DSDT.pcie | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 tests/data/acpi/microvm/DSDT.pcie diff --git a/tests/data/acpi/microvm/DSDT.pcie b/tests/data/acpi/microvm/DSDT.pcie new file mode 100644 index 0000000000..e69de29bb2 From 62b61b85527ad4460559142dc4a5cfad502a5b01 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:53 +0200 Subject: [PATCH 09/12] tests/acpi: factor out common microvm test setup ... into new test_acpi_microvm_prepare helper Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-10-kraxel@redhat.com --- tests/qtest/bios-tables-test.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 3c09b844f9..7be2b3131e 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1072,15 +1072,20 @@ static void test_acpi_virt_tcg_memhp(void) } +static void test_acpi_microvm_prepare(test_data *data) +{ + memset(data, 0, sizeof(*data)); + data->machine = "microvm"; + data->required_struct_types = NULL; /* no smbios */ + data->required_struct_types_len = 0; + data->blkdev = "virtio-blk-device"; +} + static void test_acpi_microvm_tcg(void) { test_data data; - memset(&data, 0, sizeof(data)); - data.machine = "microvm"; - data.required_struct_types = NULL; /* no smbios */ - data.required_struct_types_len = 0; - data.blkdev = "virtio-blk-device"; + test_acpi_microvm_prepare(&data); test_acpi_one(" -machine microvm,acpi=on,rtc=off", &data); free_test_data(&data); From 18bb73b3273d0c55ce1db1f8ab123d3d53506c7b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:54 +0200 Subject: [PATCH 10/12] tests/acpi: add microvm pcie test Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-11-kraxel@redhat.com --- tests/qtest/bios-tables-test.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 7be2b3131e..edf672d26f 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1091,6 +1091,18 @@ static void test_acpi_microvm_tcg(void) free_test_data(&data); } +static void test_acpi_microvm_pcie_tcg(void) +{ + test_data data; + + test_acpi_microvm_prepare(&data); + data.variant = ".pcie"; + data.tcg_only = true; /* need constant host-phys-bits */ + test_acpi_one(" -machine microvm,acpi=on,rtc=off,pcie=on", + &data); + free_test_data(&data); +} + static void test_acpi_virt_tcg_numamem(void) { test_data data = { @@ -1213,6 +1225,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat); qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat); qtest_add_func("acpi/microvm", test_acpi_microvm_tcg); + if (strcmp(arch, "x86_64") == 0) { + qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg); + } } else if (strcmp(arch, "aarch64") == 0) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); From 55c2f967c19fdbf6b19e32938ae2b3dd70389be8 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:55 +0200 Subject: [PATCH 11/12] acpi/gpex: no reason to use a method for _CRS ... just to return something which is constant anyway. - Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings - { - Return (ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, [ ... ] + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, [ ... ] Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-12-kraxel@redhat.com --- hw/pci-host/gpex-acpi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 6fb951a0c1..dbb350a837 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -57,7 +57,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(method, aml_return(aml_int(cfg->ecam.base))); aml_append(dev, method); - method = aml_method("_CRS", 0, AML_NOTSERIALIZED); Aml *rbuf = aml_resource_template(); aml_append(rbuf, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, @@ -89,8 +88,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) 0x0000, cfg->mmio64.size)); } - aml_append(method, aml_return(rbuf)); - aml_append(dev, method); + aml_append(dev, aml_name_decl("_CRS", rbuf)); /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); From 7f6c3d1a574bddcda6931eb00287089998725f71 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:56 +0200 Subject: [PATCH 12/12] tests/acpi: update expected data files Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-13-kraxel@redhat.com --- tests/data/acpi/microvm/DSDT.pcie | Bin 0 -> 3023 bytes tests/data/acpi/virt/DSDT | Bin 5200 -> 5196 bytes tests/data/acpi/virt/DSDT.memhp | Bin 6561 -> 6557 bytes tests/data/acpi/virt/DSDT.numamem | Bin 5200 -> 5196 bytes tests/qtest/bios-tables-test-allowed-diff.h | 5 ----- 5 files changed, 5 deletions(-) diff --git a/tests/data/acpi/microvm/DSDT.pcie b/tests/data/acpi/microvm/DSDT.pcie index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4b765541e372f4ba4e25529c14acf696516c8f61 100644 GIT binary patch literal 3023 zcmZveJ!~UI6vyA%>v%o>$l7tfKOE>z2(-2p9Su_KwUZdd$)4A_AbirEgg_i=B7u>USJmoBTcK$Q(y?MX4yR*{?JHy}e zM5$ZtLw_&aY`+)y9gJB-#C^WHyN7IvbrYb4M>090Z>4`FbrR(zfpoyxV$i|6p(k+ATe) zvdF@3frN8eQHzgqWKrqo7nCAGUY50}^E%)DDe!yV%lIwtZ6*K z;5;%Mlxu1&AfI~lA#IX}e+RwK=>dI!E5S%75DbQM`=6?_O5V;-r?eaPJkos&{W?_& zJg!m@jYOm&np7#;h3OQxSKD1F_JUza&&7T)O(c6FeryX=ZF{BIGcn~7Ytz^hl0A`4 zY@3cflMK?to`@QornM(b6Um;)DE72t&m;po_DoD|?U^JGX>w)+XD0ScOf%XuNgmSV zoDrP3xyUCmospc7CTCV~W(8+fazdJ%j^K0zrz1HbO-{TJMy2ss>gvVC%t=m2lT!&! zB{-Gjgfuy^d+3_P_b4wo^O6(N!Eb=d9#}G&xwKsXGL&UBqyZFIVU*h1m~RO zgfuy;g0m_(tCADaTIUzOY=)7n17WDEH?Rz`dAL8Kps9{;yt8moN zpL~7%NXDu&Q8);#t5Ev96Mx^YL*b-ghQj7`Ba|My4)rc))p$i#DkWoKJG&7}kI7ig zSH()pSlHlh#L{C|v8sj0Z@1`@Yw=8%;vl2m|F%de9wM4@V|{}+tH1|G{ymvar+?`# zZC<=#%;;&fu)x_x{m%+40BaIpvP}e>VTC zt!@8s{8{VCJAZt1aiVM(G;norZJx5=INWJ+sE6FB8n+Yo@%VxD6=v$Ob$zn%c%0bj zVV5UQ*_g*KPkt=vabBc;c~X5d>V$oJ@|w=(>FwYC4!6GSf4}%ofB9FxKgo?hq04gG zvbe#qvTqN%p?Kc-49y40rt)so=NVT8)%lmN#t&ZBB@WX~y=AYLc8xe#DNRqX~yo2YLc8xPAfJ$a^BSh86~NP`Ig DNc#-* diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp index 545a18c3657781d350a006adfa5e58fa63e63922..54728e2b4b8b959f3f829386f6a388ef2600e747 100644 GIT binary patch delta 43 zcmZ2zJlB}ZCDSh86~sFEE3 DEVvAM diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem index 9b002836f35fd03afeab9e827fdde3134d26ed2e..bc519abff9cadc1552e4e586b0a3f5f0db498f4a 100644 GIT binary patch delta 43 zcmcbhaYlp7CDBB@WX~y=AYLc8xe#DNRqX~yo2YLc8xPAfJ$a^BSh86~NP`Ig DNc#-* diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 53109c22a5..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,6 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/microvm/DSDT.pcie32", -"tests/data/acpi/microvm/DSDT.pcie64", -"tests/data/acpi/virt/DSDT", -"tests/data/acpi/virt/DSDT.numamem", -"tests/data/acpi/virt/DSDT.memhp",