mirror of https://github.com/proxmox/mirror_qemu
EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162master
parent
4de9b249d3
commit
b29a0341d7
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@ -162,7 +162,7 @@ struct CPUMIPSState {
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#define CP0Ca_EC 2
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#define CP0Ca_EC 2
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target_ulong CP0_EPC;
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target_ulong CP0_EPC;
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int32_t CP0_PRid;
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int32_t CP0_PRid;
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target_ulong CP0_EBase;
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int32_t CP0_EBase;
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int32_t CP0_Config0;
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int32_t CP0_Config0;
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#define CP0C0_M 31
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_K23 28
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@ -1158,7 +1158,7 @@ void op_mfc0_prid (void)
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void op_mfc0_ebase (void)
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void op_mfc0_ebase (void)
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{
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{
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T0 = (int32_t)env->CP0_EBase;
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T0 = env->CP0_EBase;
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RETURN();
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RETURN();
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}
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}
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@ -1423,7 +1423,7 @@ void op_mtc0_ebase (void)
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{
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{
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/* vectored interrupts not implemented */
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/* vectored interrupts not implemented */
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/* Multi-CPU not implemented */
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/* Multi-CPU not implemented */
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env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
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env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
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RETURN();
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RETURN();
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}
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}
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@ -1563,12 +1563,6 @@ void op_dmfc0_epc (void)
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RETURN();
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RETURN();
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}
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}
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void op_dmfc0_ebase (void)
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{
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T0 = env->CP0_EBase;
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RETURN();
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}
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void op_dmfc0_lladdr (void)
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void op_dmfc0_lladdr (void)
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{
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{
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T0 = env->CP0_LLAddr >> 4;
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T0 = env->CP0_LLAddr >> 4;
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@ -1627,15 +1621,6 @@ void op_dmtc0_epc (void)
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RETURN();
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RETURN();
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}
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}
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void op_dmtc0_ebase (void)
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{
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/* vectored interrupts not implemented */
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/* Multi-CPU not implemented */
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/* XXX: 64bit addressing broken */
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env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
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RETURN();
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}
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void op_dmtc0_watchlo0 (void)
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void op_dmtc0_watchlo0 (void)
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{
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{
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env->CP0_WatchLo = T0;
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env->CP0_WatchLo = T0;
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@ -3099,7 +3099,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
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rn = "PRid";
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rn = "PRid";
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break;
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break;
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case 1:
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case 1:
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gen_op_dmfc0_ebase();
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gen_op_mfc0_ebase();
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rn = "EBase";
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rn = "EBase";
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break;
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break;
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default:
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default:
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@ -3683,7 +3683,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
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rn = "PRid";
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rn = "PRid";
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break;
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break;
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case 1:
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case 1:
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gen_op_dmtc0_ebase();
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gen_op_mtc0_ebase();
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rn = "EBase";
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rn = "EBase";
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break;
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break;
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default:
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default:
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@ -5305,7 +5305,7 @@ void cpu_reset (CPUMIPSState *env)
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#endif
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#endif
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env->CP0_Wired = 0;
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env->CP0_Wired = 0;
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/* SMP not implemented */
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/* SMP not implemented */
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env->CP0_EBase = (int32_t)0x80000000;
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env->CP0_EBase = 0x80000000;
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env->CP0_Config0 = MIPS_CONFIG0;
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env->CP0_Config0 = MIPS_CONFIG0;
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env->CP0_Config1 = MIPS_CONFIG1;
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env->CP0_Config1 = MIPS_CONFIG1;
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env->CP0_Config2 = MIPS_CONFIG2;
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env->CP0_Config2 = MIPS_CONFIG2;
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