mirror of https://github.com/proxmox/mirror_qemu
Hexagon (gdbstub): add HVX support
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Co-authored-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com>master
Taylor Simpson
parent
b0bd9d8adf
commit
b647652ee5
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@ -1,2 +1,2 @@
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TARGET_ARCH=hexagon
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TARGET_XML_FILES=gdb-xml/hexagon-core.xml
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TARGET_XML_FILES=gdb-xml/hexagon-core.xml gdb-xml/hexagon-hvx.xml
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@ -0,0 +1,96 @@
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<?xml version="1.0"?>
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<!--
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Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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This work is licensed under the terms of the GNU GPL, version 2 or
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(at your option) any later version. See the COPYING file in the
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top-level directory.
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Note: this file is intended to be use with LLDB, so it contains fields
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that may be unknown to GDB. For more information on such fields, please
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see:
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https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/docs/lldb-gdb-remote.txt#L738-L860
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https://github.com/llvm/llvm-project/blob/287aa6c4536408413b860e61fca0318a27214cf3/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp#L4275-L4335
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-->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.hexagon.hvx">
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<vector id="vud" type="uint64" count="16"/>
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<vector id="vd" type="int64" count="16"/>
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<vector id="vuw" type="uint32" count="32"/>
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<vector id="vw" type="int32" count="32"/>
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<vector id="vuh" type="uint16" count="64"/>
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<vector id="vh" type="int16" count="64"/>
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<vector id="vub" type="uint8" count="128"/>
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<vector id="vb" type="int8" count="128"/>
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<union id="hex_vec">
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<field name="ud" type="vud"/>
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<field name="d" type="vd"/>
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<field name="uw" type="vuw"/>
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<field name="w" type="vw"/>
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<field name="uh" type="vuh"/>
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<field name="h" type="vh"/>
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<field name="ub" type="vub"/>
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<field name="b" type="vb"/>
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</union>
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<flags id="ui2" size="1">
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<field name="0" start="0" end="0"/>
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<field name="1" start="1" end="1"/>
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</flags>
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<flags id="ui4" size="1">
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<field name="0" start="0" end="0"/>
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<field name="1" start="1" end="1"/>
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<field name="2" start="2" end="2"/>
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<field name="3" start="3" end="3"/>
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</flags>
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<vector id="vpd" type="uint8" count="16"/>
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<vector id="vpw" type="ui4" count="32"/>
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<vector id="vph" type="ui2" count="64"/>
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<vector id="vpb" type="bool" count="128"/>
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<union id="hex_vec_pred">
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<field name="d" type="vpd"/>
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<field name="w" type="vpw"/>
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<field name="h" type="vph"/>
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<field name="b" type="vpb"/>
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</union>
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<reg name="v0" bitsize="1024" offset="256" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="88"/>
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<reg name="v1" bitsize="1024" offset="384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="89"/>
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<reg name="v2" bitsize="1024" offset="512" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="90"/>
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<reg name="v3" bitsize="1024" offset="640" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="91"/>
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<reg name="v4" bitsize="1024" offset="768" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="92"/>
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<reg name="v5" bitsize="1024" offset="896" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="93"/>
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<reg name="v6" bitsize="1024" offset="1024" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="94"/>
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<reg name="v7" bitsize="1024" offset="1152" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="95"/>
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<reg name="v8" bitsize="1024" offset="1280" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="96"/>
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<reg name="v9" bitsize="1024" offset="1408" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="97"/>
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<reg name="v10" bitsize="1024" offset="1536" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="98"/>
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<reg name="v11" bitsize="1024" offset="1664" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="99"/>
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<reg name="v12" bitsize="1024" offset="1792" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="100"/>
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<reg name="v13" bitsize="1024" offset="1920" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="101"/>
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<reg name="v14" bitsize="1024" offset="2048" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="102"/>
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<reg name="v15" bitsize="1024" offset="2176" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="103"/>
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<reg name="v16" bitsize="1024" offset="2304" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="104"/>
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<reg name="v17" bitsize="1024" offset="2432" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="105"/>
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<reg name="v18" bitsize="1024" offset="2560" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="106"/>
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<reg name="v19" bitsize="1024" offset="2688" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="107"/>
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<reg name="v20" bitsize="1024" offset="2816" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="108"/>
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<reg name="v21" bitsize="1024" offset="2944" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="109"/>
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<reg name="v22" bitsize="1024" offset="3072" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="110"/>
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<reg name="v23" bitsize="1024" offset="3200" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="111"/>
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<reg name="v24" bitsize="1024" offset="3328" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="112"/>
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<reg name="v25" bitsize="1024" offset="3456" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="113"/>
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<reg name="v26" bitsize="1024" offset="3584" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="114"/>
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<reg name="v27" bitsize="1024" offset="3712" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="115"/>
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<reg name="v28" bitsize="1024" offset="3840" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="116"/>
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<reg name="v29" bitsize="1024" offset="3968" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="117"/>
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<reg name="v30" bitsize="1024" offset="4096" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="118"/>
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<reg name="v31" bitsize="1024" offset="4224" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="119"/>
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<reg name="q0" bitsize="128" offset="4352" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="120"/>
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<reg name="q1" bitsize="128" offset="4368" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="121"/>
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<reg name="q2" bitsize="128" offset="4384" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="122"/>
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<reg name="q3" bitsize="128" offset="4400" encoding="vector" format="hex" group="HVX Vector Registers" dwarf_regnum="123"/>
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</feature>
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@ -24,6 +24,7 @@
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#include "hw/qdev-properties.h"
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#include "fpu/softfloat-helpers.h"
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#include "tcg/tcg.h"
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#include "exec/gdbstub.h"
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static void hexagon_v67_cpu_init(Object *obj) { }
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static void hexagon_v68_cpu_init(Object *obj) { }
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@ -339,6 +340,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
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return;
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}
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gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
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hexagon_hvx_gdb_write_register,
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NUM_VREGS + NUM_QREGS,
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"hexagon-hvx.xml", 0);
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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@ -60,3 +60,71 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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g_assert_not_reached();
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}
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static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
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{
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int total = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
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total += gdb_get_regl(mem_buf, env->VRegs[n].uw[i]);
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}
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return total;
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}
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static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
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{
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int total = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
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total += gdb_get_regl(mem_buf, env->QRegs[n].uw[i]);
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}
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return total;
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}
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int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n)
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{
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if (n < NUM_VREGS) {
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return gdb_get_vreg(env, mem_buf, n);
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}
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n -= NUM_VREGS;
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if (n < NUM_QREGS) {
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return gdb_get_qreg(env, mem_buf, n);
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}
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g_assert_not_reached();
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}
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static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
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env->VRegs[n].uw[i] = ldtul_p(mem_buf);
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mem_buf += 4;
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}
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return MAX_VEC_SIZE_BYTES;
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}
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static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
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env->QRegs[n].uw[i] = ldtul_p(mem_buf);
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mem_buf += 4;
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}
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return MAX_VEC_SIZE_BYTES / 8;
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}
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int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n)
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{
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if (n < NUM_VREGS) {
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return gdb_put_vreg(env, mem_buf, n);
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}
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n -= NUM_VREGS;
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if (n < NUM_QREGS) {
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return gdb_put_qreg(env, mem_buf, n);
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}
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g_assert_not_reached();
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}
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@ -33,6 +33,8 @@
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int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n);
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int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n);
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void hexagon_debug_vreg(CPUHexagonState *env, int regnum);
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void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
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