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tcg: Define "deposit" as an optional operation. 

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
master
Richard Henderson 2011-01-10 19:23:42 -08:00 committed by Edgar E. Iglesias
parent 9f8beb6636
commit b7767f0f3c
3 changed files with 84 additions and 0 deletions
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14
tcg/README
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@ -285,6 +285,20 @@ the four high order bytes are set to zero.
Indicate that the value of t0 won't be used later. It is useful to Indicate that the value of t0 won't be used later. It is useful to
force dead code elimination. force dead code elimination.
* deposit_i32/i64 dest, t1, t2, pos, loc
Deposit T2 as a bitfield into T1, placing the result in DEST.
The bitfield is described by POS/LOC, which are immediate values:
LEN - the length of the bitfield
POS - the position of the first bit, counting from the LSB
For example, pos=8, len=4 indicates a 4-bit field at bit 8.
This operation would be equivalent to
dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
********* Conditional moves ********* Conditional moves
* setcond_i32/i64 cond, dest, t1, t2 * setcond_i32/i64 cond, dest, t1, t2

64
tcg/tcg-op.h
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@ -254,6 +254,30 @@ static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg5; *gen_opparam_ptr++ = arg5;
} }
static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
TCGv_i32 arg2, TCGv_i32 arg3,
TCGArg arg4, TCGArg arg5)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
*gen_opparam_ptr++ = arg4;
*gen_opparam_ptr++ = arg5;
}
static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
TCGv_i64 arg2, TCGv_i64 arg3,
TCGArg arg4, TCGArg arg5)
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
*gen_opparam_ptr++ = arg4;
*gen_opparam_ptr++ = arg5;
}
static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
TCGv_i32 arg6) TCGv_i32 arg6)
@ -2071,6 +2095,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} }
} }
static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
TCGv_i32 arg2, unsigned int ofs,
unsigned int len)
{
#ifdef TCG_TARGET_HAS_deposit_i32
tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
#else
uint32_t mask = (1u << len) - 1;
TCGv_i32 t1 = tcg_temp_new_i32 ();
tcg_gen_andi_i32(t1, arg2, mask);
tcg_gen_shli_i32(t1, t1, ofs);
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
tcg_gen_or_i32(ret, ret, t1);
tcg_temp_free_i32(t1);
#endif
}
static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2, unsigned int ofs,
unsigned int len)
{
#ifdef TCG_TARGET_HAS_deposit_i64
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
#else
uint64_t mask = (1ull << len) - 1;
TCGv_i64 t1 = tcg_temp_new_i64 ();
tcg_gen_andi_i64(t1, arg2, mask);
tcg_gen_shli_i64(t1, t1, ofs);
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
tcg_gen_or_i64(ret, ret, t1);
tcg_temp_free_i64(t1);
#endif
}
/***************************************/ /***************************************/
/* QEMU specific operations. Their type depend on the QEMU CPU /* QEMU specific operations. Their type depend on the QEMU CPU
type. */ type. */
@ -2384,6 +2446,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i64 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
#define tcg_gen_rotr_tl tcg_gen_rotr_i64 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
#define tcg_gen_rotri_tl tcg_gen_rotri_i64 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
#define tcg_const_tl tcg_const_i64 #define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64 #define tcg_const_local_tl tcg_const_local_i64
#else #else
@ -2454,6 +2517,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i32 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
#define tcg_const_tl tcg_const_i32 #define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32 #define tcg_const_local_tl tcg_const_local_i32
#endif #endif

6
tcg/tcg-opc.h
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@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, 0) DEF(rotl_i32, 1, 2, 0, 0)
DEF(rotr_i32, 1, 2, 0, 0) DEF(rotr_i32, 1, 2, 0, 0)
#endif #endif
#ifdef TCG_TARGET_HAS_deposit_i32
DEF(deposit_i32, 1, 2, 2, 0)
#endif
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
@ -168,6 +171,9 @@ DEF(sar_i64, 1, 2, 0, 0)
DEF(rotl_i64, 1, 2, 0, 0) DEF(rotl_i64, 1, 2, 0, 0)
DEF(rotr_i64, 1, 2, 0, 0) DEF(rotr_i64, 1, 2, 0, 0)
#endif #endif
#ifdef TCG_TARGET_HAS_deposit_i64
DEF(deposit_i64, 1, 2, 2, 0)
#endif
DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#ifdef TCG_TARGET_HAS_ext8s_i64 #ifdef TCG_TARGET_HAS_ext8s_i64