mirror of https://github.com/proxmox/mirror_qemu
initial user mmu support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162master
parent
4955a2cd16
commit
b8a9e8f133
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@ -24,8 +24,10 @@
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#include "cpu-defs.h"
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#include "cpu-defs.h"
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_SWI 2 /* software interrupt */
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#define EXCP_SWI 2 /* software interrupt */
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#define EXCP_PREFETCH_ABORT 3
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#define EXCP_DATA_ABORT 4
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typedef struct CPUARMState {
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typedef struct CPUARMState {
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uint32_t regs[16];
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uint32_t regs[16];
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@ -39,6 +41,9 @@ typedef struct CPUARMState {
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int thumb; /* 0 = arm mode, 1 = thumb mode */
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int thumb; /* 0 = arm mode, 1 = thumb mode */
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/* coprocessor 15 (MMU) status */
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uint32_t cp15_6;
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/* exception/interrupt handling */
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/* exception/interrupt handling */
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jmp_buf jmp_env;
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jmp_buf jmp_env;
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int exception_index;
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int exception_index;
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@ -48,3 +48,6 @@ static inline void env_to_regs(void)
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static inline void regs_to_env(void)
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static inline void regs_to_env(void)
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{
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{
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}
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}
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu);
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@ -424,6 +424,7 @@ static void disas_arm_insn(DisasContext *s)
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gen_op_movl_T0_psr();
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gen_op_movl_T0_psr();
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gen_movl_reg_T0(s, rd);
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gen_movl_reg_T0(s, rd);
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}
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}
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break;
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case 0x1:
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case 0x1:
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if (op1 == 1) {
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if (op1 == 1) {
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/* branch/exchange thumb (bx). */
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/* branch/exchange thumb (bx). */
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@ -1576,3 +1577,23 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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{
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return addr;
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return addr;
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}
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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env->cp15_6 = address;
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if (rw == 2) {
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env->exception_index = EXCP_PREFETCH_ABORT;
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} else {
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env->exception_index = EXCP_DATA_ABORT;
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}
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return 1;
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}
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#else
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#error not implemented
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#endif
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