mirror of https://github.com/proxmox/mirror_qemu
Initial SPARC SMP support (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1694 c046a42c-6fe2-441c-8c8c-71466251a162master
bellard
parent
b9788fc4c4
commit
ba3c64fb47
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@ -16,6 +16,7 @@ version 0.7.3:
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- MIPS User Linux emulation
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- MIPS fixes to boot Linux (Daniel Jacobowitz)
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- NX bit support
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- Initial SPARC SMP support (Blue Swirl)
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version 0.7.2:
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@ -734,6 +734,7 @@ extern int code_copy_enabled;
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#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
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#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
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#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
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#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
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void cpu_interrupt(CPUState *s, int mask);
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void cpu_reset_interrupt(CPUState *env, int mask);
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14
cpu-exec.c
14
cpu-exec.c
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@ -274,6 +274,15 @@ int cpu_exec(CPUState *env1)
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return EXCP_HALTED;
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}
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}
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#elif defined(TARGET_SPARC)
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if (env1->halted) {
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env1->psret != 0)) {
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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}
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}
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#elif defined(TARGET_ARM)
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if (env1->halted) {
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/* An interrupt wakes the CPU even if the I and F CPSR bits are
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@ -522,7 +531,10 @@ int cpu_exec(CPUState *env1)
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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//do_interrupt(0, 0, 0, 0, 0);
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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} else if (interrupt_request & CPU_INTERRUPT_HALT) {
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env1->halted = 1;
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return EXCP_HALTED;
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}
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#elif defined(TARGET_ARM)
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if (interrupt_request & CPU_INTERRUPT_FIQ
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&& !(env->uncached_cpsr & CPSR_F)) {
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@ -53,6 +53,7 @@ typedef struct SLAVIO_INTCTLState {
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count[32];
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#endif
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CPUState *cpu_envs[MAX_CPUS];
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} SLAVIO_INTCTLState;
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#define INTCTL_MAXADDR 0xf
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@ -96,6 +97,7 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint
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case 2: // set softint
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val &= 0xfffe0000;
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s->intreg_pending[cpu] |= val;
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slavio_check_interrupts(s);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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break;
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default:
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@ -216,7 +218,7 @@ static void slavio_check_interrupts(void *opaque)
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CPUState *env;
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SLAVIO_INTCTLState *s = opaque;
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uint32_t pending = s->intregm_pending;
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unsigned int i, max = 0;
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unsigned int i, j, max = 0;
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pending &= ~s->intregm_disabled;
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@ -227,20 +229,52 @@ static void slavio_check_interrupts(void *opaque)
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max = intbit_to_level[i];
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}
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}
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env = first_cpu;
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered pil %d\n", max);
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env = s->cpu_envs[s->target_cpu];
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if (!env) {
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DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
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}
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else {
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if (env->halted)
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env->halted = 0;
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[max]++;
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s->irq_count[max]++;
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#endif
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env->interrupt_index = TT_EXTINT | max;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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env->interrupt_index = TT_EXTINT | max;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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else
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DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
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}
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else
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DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
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}
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else
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DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
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for (i = 0; i < MAX_CPUS; i++) {
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max = 0;
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env = s->cpu_envs[i];
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if (!env)
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continue;
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for (j = 17; j < 32; j++) {
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if (s->intreg_pending[i] & (1 << j)) {
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if (max < j - 16)
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max = j - 16;
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}
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}
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if (max > 0) {
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if (env->halted)
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env->halted = 0;
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[max]++;
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#endif
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env->interrupt_index = TT_EXTINT | max;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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}
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}
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/*
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@ -251,7 +285,7 @@ void slavio_pic_set_irq(void *opaque, int irq, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set irq %d level %d\n", irq, level);
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DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
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if (irq < 32) {
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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@ -269,6 +303,29 @@ void slavio_pic_set_irq(void *opaque, int irq, int level)
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slavio_check_interrupts(s);
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}
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void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
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if (cpu == (unsigned int)-1) {
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slavio_pic_set_irq(opaque, irq, level);
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return;
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}
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if (irq < 32) {
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uint32_t pil = intbit_to_level[irq];
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if (pil > 0) {
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if (level) {
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s->intreg_pending[cpu] |= 1 << pil;
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}
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else {
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s->intreg_pending[cpu] &= ~(1 << pil);
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}
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}
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}
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slavio_check_interrupts(s);
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}
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static void slavio_intctl_save(QEMUFile *f, void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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@ -312,6 +369,12 @@ static void slavio_intctl_reset(void *opaque)
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s->target_cpu = 0;
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}
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void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
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{
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SLAVIO_INTCTLState *s = opaque;
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s->cpu_envs[cpu] = env;
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}
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void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
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{
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int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
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@ -124,9 +124,8 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32
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case 0xa000000:
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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#if 0
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// XXX: halting CPU does not work
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raise_exception(EXCP_HLT);
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cpu_loop_exit();
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// XXX almost works
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
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#endif
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break;
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}
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@ -45,6 +45,8 @@
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#ifdef DEBUG_SERIAL
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#define SER_DPRINTF(fmt, args...) \
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do { printf("SER: " fmt , ##args); } while (0)
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#define pic_set_irq(irq, level) \
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do { printf("SER: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
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#else
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#define SER_DPRINTF(fmt, args...)
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#endif
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@ -174,6 +176,50 @@ static void slavio_serial_reset(void *opaque)
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slavio_serial_reset_chn(&s->chn[1]);
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}
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static inline void clr_rxint(ChannelState *s)
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{
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s->rxint = 0;
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if (s->chn == 0)
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s->rregs[3] &= ~0x20;
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else {
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s->otherchn->rregs[3] &= ~4;
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}
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slavio_serial_update_irq(s);
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}
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static inline void set_rxint(ChannelState *s)
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{
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s->rxint = 1;
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if (s->chn == 0)
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s->rregs[3] |= 0x20;
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else {
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s->otherchn->rregs[3] |= 4;
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}
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slavio_serial_update_irq(s);
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}
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static inline void clr_txint(ChannelState *s)
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{
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s->txint = 0;
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if (s->chn == 0)
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s->rregs[3] &= ~0x10;
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else {
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s->otherchn->rregs[3] &= ~2;
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}
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slavio_serial_update_irq(s);
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}
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static inline void set_txint(ChannelState *s)
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{
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s->txint = 1;
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if (s->chn == 0)
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s->rregs[3] |= 0x10;
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else {
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s->otherchn->rregs[3] |= 2;
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}
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slavio_serial_update_irq(s);
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}
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static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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SerialState *ser = opaque;
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@ -198,10 +244,14 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint
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newreg |= 0x8;
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break;
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case 0x20:
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s->rxint = 0;
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clr_rxint(s);
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break;
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case 0x28:
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s->txint = 0;
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clr_txint(s);
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break;
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case 0x38:
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clr_rxint(s);
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clr_txint(s);
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break;
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default:
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break;
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@ -247,12 +297,7 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint
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s->txint = 1;
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s->rregs[0] |= 4; // Tx buffer empty
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s->rregs[1] |= 1; // All sent
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// Interrupts reported only on channel A
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if (s->chn == 0)
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s->rregs[3] |= 0x10;
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else {
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s->otherchn->rregs[3] |= 2;
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}
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set_txint(s);
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slavio_serial_update_irq(s);
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}
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break;
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@ -280,6 +325,7 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
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return ret;
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case 1:
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s->rregs[0] &= ~1;
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clr_rxint(s);
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if (s->type == kbd)
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ret = get_queue(s);
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else
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@ -304,16 +350,10 @@ static int serial_can_receive(void *opaque)
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static void serial_receive_byte(ChannelState *s, int ch)
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{
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SER_DPRINTF("put ch %d\n", ch);
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s->rregs[0] |= 1;
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// Interrupts reported only on channel A
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if (s->chn == 0)
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s->rregs[3] |= 0x20;
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else {
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s->otherchn->rregs[3] |= 4;
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}
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s->rx = ch;
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s->rxint = 1;
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slavio_serial_update_irq(s);
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set_rxint(s);
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}
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static void serial_receive_break(ChannelState *s)
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@ -42,6 +42,9 @@ do { printf("TIMER: " fmt , ##args); } while (0)
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* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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* are zero. Bit 31 is 1 when count has been reached.
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*
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* Per-CPU timers interrupt local CPU, system timer uses normal
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* interrupt routing.
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*
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*/
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typedef struct SLAVIO_TIMERState {
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@ -53,11 +56,11 @@ typedef struct SLAVIO_TIMERState {
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int irq;
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int reached, stopped;
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int mode; // 0 = processor, 1 = user, 2 = system
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unsigned int cpu;
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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#define CNT_FREQ 2000000
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#define MAX_CPUS 16
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// Update count, set irq, update expire_time
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static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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@ -73,7 +76,7 @@ static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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else
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ticks = qemu_get_clock(vm_clock) - s->tick_offset;
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out = (ticks >= s->expire_time);
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out = (ticks > s->expire_time);
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if (out)
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s->reached = 0x80000000;
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if (!s->limit)
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@ -100,7 +103,7 @@ static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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DPRINTF("irq %d limit %d reached %d d %lld count %d s->c %x diff %lld stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
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if (s->mode != 1)
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pic_set_irq(s->irq, out);
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pic_set_irq_cpu(s->irq, out, s->cpu);
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}
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// timer callback
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@ -127,7 +130,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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// part of counter (user mode)
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if (s->mode != 1) {
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// clear irq
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pic_set_irq(s->irq, 0);
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pic_set_irq_cpu(s->irq, 0, s->cpu);
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s->count_load_time = qemu_get_clock(vm_clock);
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s->reached = 0;
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return s->limit;
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@ -263,7 +266,7 @@ static void slavio_timer_reset(void *opaque)
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slavio_timer_get_out(s);
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}
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static void slavio_timer_init_internal(uint32_t addr, int irq, int mode)
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void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu)
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{
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int slavio_timer_io_memory;
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SLAVIO_TIMERState *s;
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@ -273,6 +276,7 @@ static void slavio_timer_init_internal(uint32_t addr, int irq, int mode)
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return;
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s->irq = irq;
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s->mode = mode;
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s->cpu = cpu;
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s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
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slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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@ -282,14 +286,3 @@ static void slavio_timer_init_internal(uint32_t addr, int irq, int mode)
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qemu_register_reset(slavio_timer_reset, s);
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slavio_timer_reset(s);
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}
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void slavio_timer_init(uint32_t addr1, int irq1, uint32_t addr2, int irq2)
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{
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_timer_init_internal(addr1 + i * TARGET_PAGE_SIZE, irq1, 0);
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}
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slavio_timer_init_internal(addr2, irq2, 2);
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}
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32
hw/sun4m.c
32
hw/sun4m.c
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@ -56,6 +56,7 @@
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#define PHYS_JJ_FDC 0x71400000 /* Floppy */
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#define PHYS_JJ_FLOPPY_IRQ 22
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#define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
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#define MAX_CPUS 16
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/* TSC handling */
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@ -128,6 +129,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
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// NVRAM_size, arch not applicable
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m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
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m48t59_write(nvram, 0x2E, 0);
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m48t59_write(nvram, 0x2F, nographic & 0xff);
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nvram_set_lword(nvram, 0x30, RAM_size);
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m48t59_write(nvram, 0x34, boot_device & 0xff);
|
||||
|
|
@ -179,6 +182,11 @@ void pic_set_irq(int irq, int level)
|
|||
slavio_pic_set_irq(slavio_intctl, irq, level);
|
||||
}
|
||||
|
||||
void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
|
||||
{
|
||||
slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
|
||||
}
|
||||
|
||||
static void *tcx;
|
||||
|
||||
void vga_update_display()
|
||||
|
|
@ -222,7 +230,7 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename)
|
||||
{
|
||||
CPUState *env;
|
||||
CPUState *env, *envs[MAX_CPUS];
|
||||
char buf[1024];
|
||||
int ret, linux_boot;
|
||||
unsigned int i;
|
||||
|
|
@ -230,19 +238,31 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
|
||||
linux_boot = (kernel_filename != NULL);
|
||||
|
||||
env = cpu_init();
|
||||
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
|
||||
qemu_register_reset(main_cpu_reset, env);
|
||||
|
||||
/* init CPUs */
|
||||
for(i = 0; i < smp_cpus; i++) {
|
||||
env = cpu_init();
|
||||
envs[i] = env;
|
||||
if (i != 0)
|
||||
env->halted = 1;
|
||||
register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
|
||||
qemu_register_reset(main_cpu_reset, env);
|
||||
}
|
||||
/* allocate RAM */
|
||||
cpu_register_physical_memory(0, ram_size, 0);
|
||||
|
||||
iommu = iommu_init(PHYS_JJ_IOMMU);
|
||||
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
|
||||
for(i = 0; i < smp_cpus; i++) {
|
||||
slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
|
||||
}
|
||||
|
||||
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
|
||||
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
|
||||
nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
|
||||
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
|
||||
for (i = 0; i < MAX_CPUS; i++) {
|
||||
slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
|
||||
}
|
||||
slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
|
||||
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
|
||||
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
||||
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
||||
|
|
|
|||
|
|
@ -259,6 +259,10 @@ static void do_info_cpus(void)
|
|||
term_printf(" nip=0x" TARGET_FMT_lx, env->nip);
|
||||
if (env->halted)
|
||||
term_printf(" (halted)");
|
||||
#elif defined(TARGET_SPARC)
|
||||
term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
|
||||
if (env->halted)
|
||||
term_printf(" (halted)");
|
||||
#endif
|
||||
term_printf("\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ typedef struct CPUSPARCState {
|
|||
int exception_index;
|
||||
int interrupt_index;
|
||||
int interrupt_request;
|
||||
int halted;
|
||||
/* NOTE: we allow 8 more registers to handle wrapping */
|
||||
target_ulong regbase[NWINDOWS * 16 + 8];
|
||||
|
||||
|
|
|
|||
7
vl.c
7
vl.c
|
|
@ -153,6 +153,11 @@ USBPort *vm_usb_ports[MAX_VM_USB_PORTS];
|
|||
USBDevice *vm_usb_hub;
|
||||
static VLANState *first_vlan;
|
||||
int smp_cpus = 1;
|
||||
#ifdef TARGET_SPARC
|
||||
#define MAX_CPUS 16
|
||||
#else
|
||||
#define MAX_CPUS 8
|
||||
#endif
|
||||
|
||||
/***********************************************************/
|
||||
/* x86 ISA bus support */
|
||||
|
|
@ -4547,7 +4552,7 @@ int main(int argc, char **argv)
|
|||
break;
|
||||
case QEMU_OPTION_smp:
|
||||
smp_cpus = atoi(optarg);
|
||||
if (smp_cpus < 1 || smp_cpus > 8) {
|
||||
if (smp_cpus < 1 || smp_cpus > MAX_CPUS) {
|
||||
fprintf(stderr, "Invalid number of CPUs\n");
|
||||
exit(1);
|
||||
}
|
||||
|
|
|
|||
5
vl.h
5
vl.h
|
|
@ -806,6 +806,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
|
|||
/* sun4m.c */
|
||||
extern QEMUMachine sun4m_machine;
|
||||
uint32_t iommu_translate(uint32_t addr);
|
||||
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
|
||||
|
||||
/* iommu.c */
|
||||
void *iommu_init(uint32_t addr);
|
||||
|
|
@ -823,16 +824,18 @@ void tcx_screen_dump(void *opaque, const char *filename);
|
|||
|
||||
/* slavio_intctl.c */
|
||||
void *slavio_intctl_init();
|
||||
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
|
||||
void slavio_pic_info(void *opaque);
|
||||
void slavio_irq_info(void *opaque);
|
||||
void slavio_pic_set_irq(void *opaque, int irq, int level);
|
||||
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
|
||||
|
||||
/* magic-load.c */
|
||||
int load_elf(const char *filename, uint8_t *addr);
|
||||
int load_aout(const char *filename, uint8_t *addr);
|
||||
|
||||
/* slavio_timer.c */
|
||||
void slavio_timer_init(uint32_t addr1, int irq1, uint32_t addr2, int irq2);
|
||||
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu);
|
||||
|
||||
/* slavio_serial.c */
|
||||
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2);
|
||||
|
|
|
|||
Loading…
Reference in New Issue