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hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix 

QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q'
suffix for 64-bit accesses. Rename the current 'll' suffix to
have the GIC dist accessors better match the rest of the codebase.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210826180704.2131949-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Philippe Mathieu-Daudé 2021-08-26 20:07:03 +02:00 committed by Peter Maydell
parent 57469ed384
commit c0bb7d6114
1 changed files with 6 additions and 6 deletions
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12
hw/intc/arm_gicv3_dist.c
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@ -763,8 +763,8 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
}
}
static MemTxResult gicd_writell(GICv3State *s, hwaddr offset,
uint64_t value, MemTxAttrs attrs)
static MemTxResult gicd_writeq(GICv3State *s, hwaddr offset,
uint64_t value, MemTxAttrs attrs)
{
/* Our only 64-bit registers are GICD_IROUTER<n> */
int irq;
@ -779,8 +779,8 @@ static MemTxResult gicd_writell(GICv3State *s, hwaddr offset,
}
}
static MemTxResult gicd_readll(GICv3State *s, hwaddr offset,
uint64_t *data, MemTxAttrs attrs)
static MemTxResult gicd_readq(GICv3State *s, hwaddr offset,
uint64_t *data, MemTxAttrs attrs)
{
/* Our only 64-bit registers are GICD_IROUTER<n> */
int irq;
@ -812,7 +812,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
r = gicd_readl(s, offset, data, attrs);
break;
case 8:
r = gicd_readll(s, offset, data, attrs);
r = gicd_readq(s, offset, data, attrs);
break;
default:
r = MEMTX_ERROR;
@ -854,7 +854,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
r = gicd_writel(s, offset, data, attrs);
break;
case 8:
r = gicd_writell(s, offset, data, attrs);
r = gicd_writeq(s, offset, data, attrs);
break;
default:
r = MEMTX_ERROR;