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hw/timer/hpet: Convert DPRINTF to trace events 

This conversion is pretty straight-forward. Standardized some formatting
so the +0 and +4 offset cases can recycle the same message.

Signed-off-by: Daniel Hoffman <dhoff749@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231118231129.2840388-1-dhoff749@gmail.com>
[PMD: Fixed few string formats]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
master
Daniel Hoffman 2023-11-18 15:11:29 -08:00 committed by Philippe Mathieu-Daudé
parent 88cf5fec91
commit c0d0b716ba
2 changed files with 37 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
hw/timer/hpet.c
View File

@ -39,13 +39,7 @@
#include "hw/timer/i8254.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
//#define HPET_DEBUG
#ifdef HPET_DEBUG
#define DPRINTF printf
#else
#define DPRINTF(...)
#endif
#include "trace.h"
#define HPET_MSI_SUPPORT 0
@ -431,7 +425,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
HPETState *s = opaque;
uint64_t cur_tick, index;
DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
trace_hpet_ram_read(addr);
index = addr;
/*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) {
@ -439,7 +433,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
HPETTimer *timer = &s->timer[timer_id];
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
trace_hpet_timer_id_out_of_range(timer_id);
return 0;
}
@ -457,7 +451,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
case HPET_TN_ROUTE + 4:
return timer->fsb >> 32;
default:
DPRINTF("qemu: invalid hpet_ram_readl\n");
trace_hpet_ram_read_invalid();
break;
}
} else {
@ -469,7 +463,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
case HPET_CFG:
return s->config;
case HPET_CFG + 4:
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
trace_hpet_invalid_hpet_cfg(4);
return 0;
case HPET_COUNTER:
if (hpet_enabled(s)) {
@ -477,7 +471,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
} else {
cur_tick = s->hpet_counter;
}
DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
trace_hpet_ram_read_reading_counter(0, cur_tick);
return cur_tick;
case HPET_COUNTER + 4:
if (hpet_enabled(s)) {
@ -485,12 +479,12 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
} else {
cur_tick = s->hpet_counter;
}
DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
trace_hpet_ram_read_reading_counter(4, cur_tick);
return cur_tick >> 32;
case HPET_STATUS:
return s->isr;
default:
DPRINTF("qemu: invalid hpet_ram_readl\n");
trace_hpet_ram_read_invalid();
break;
}
}
@ -504,8 +498,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
HPETState *s = opaque;
uint64_t old_val, new_val, val, index;
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = 0x%" PRIx64 "\n",
addr, value);
trace_hpet_ram_write(addr, value);
index = addr;
old_val = hpet_ram_read(opaque, addr, 4);
new_val = value;
@ -515,14 +508,14 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id);
trace_hpet_ram_write_timer_id(timer_id);
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
trace_hpet_timer_id_out_of_range(timer_id);
return;
}
switch ((addr - 0x100) % 0x20) {
case HPET_TN_CFG:
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
trace_hpet_ram_write_tn_cfg();
if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
update_irq(timer, 0);
}
@ -540,10 +533,10 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
}
break;
case HPET_TN_CFG + 4: // Interrupt capabilities
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
trace_hpet_ram_write_invalid_tn_cfg(4);
break;
case HPET_TN_CMP: // comparator register
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
trace_hpet_ram_write_tn_cmp(0);
if (timer->config & HPET_TN_32BIT) {
new_val = (uint32_t)new_val;
}
@ -566,7 +559,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
}
break;
case HPET_TN_CMP + 4: // comparator register high order
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
trace_hpet_ram_write_tn_cmp(4);
if (!timer_is_periodic(timer)
|| (timer->config & HPET_TN_SETVAL)) {
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
@ -591,7 +584,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
trace_hpet_ram_write_invalid();
break;
}
return;
@ -631,7 +624,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
}
break;
case HPET_CFG + 4:
DPRINTF("qemu: invalid HPET_CFG+4 write\n");
trace_hpet_invalid_hpet_cfg(4);
break;
case HPET_STATUS:
val = new_val & s->isr;
@ -643,24 +636,20 @@ static void hpet_ram_write(void *opaque, hwaddr addr,
break;
case HPET_COUNTER:
if (hpet_enabled(s)) {
DPRINTF("qemu: Writing counter while HPET enabled!\n");
trace_hpet_ram_write_counter_write_while_enabled();
}
s->hpet_counter =
(s->hpet_counter & 0xffffffff00000000ULL) | value;
DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64 " -> "
"%" PRIx64 "\n", value, s->hpet_counter);
trace_hpet_ram_write_counter_written(0, value, s->hpet_counter);
break;
case HPET_COUNTER + 4:
if (hpet_enabled(s)) {
DPRINTF("qemu: Writing counter while HPET enabled!\n");
}
trace_hpet_ram_write_counter_write_while_enabled();
s->hpet_counter =
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64 " -> "
"%" PRIx64 "\n", value, s->hpet_counter);
trace_hpet_ram_write_counter_written(4, value, s->hpet_counter);
break;
default:
DPRINTF("qemu: invalid hpet_ram_writel\n");
trace_hpet_ram_write_invalid();
break;
}
}

15
hw/timer/trace-events
View File

@ -99,3 +99,18 @@ sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address
sh_timer_start_stop(int enable, int current) "%d (%d)"
sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64
sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64
# hpet.c
hpet_timer_id_out_of_range(uint8_t timer_id) "timer id out of range: 0x%" PRIx8
hpet_invalid_hpet_cfg(uint8_t reg_off) "invalid HPET_CFG + %u" PRIx8
hpet_ram_read(uint64_t addr) "enter hpet_ram_readl at 0x%" PRIx64
hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0x%" PRIx64
hpet_ram_read_invalid(void) "invalid hpet_ram_readl"
hpet_ram_write(uint64_t addr, uint64_t value) "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64
hpet_ram_write_timer_id(uint64_t timer_id) "hpet_ram_writel timer_id = 0x%" PRIx64
hpet_ram_write_tn_cfg(void) "hpet_ram_writel HPET_TN_CFG"
hpet_ram_write_invalid_tn_cfg(uint8_t reg_off) "invalid HPET_TN_CFG + %" PRIu8 " write"
hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8
hpet_ram_write_invalid(void) "invalid hpet_ram_writel"
hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!"
hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter) "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64