mirror of https://github.com/proxmox/mirror_qemu
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1 iQIcBAABAgAGBQJWPQcoAAoJEH3vgQaq/DkO0usP/2GxveZ01ABrE8Dh3/tVkLNS U+1UsgewYK6ZsNk4o3C328xM6a+e0AS9XiAH6QQJN2B7teI2Kp8bDUObhFe6pkZq Zy5+PvhNvMH+oUhU8louNtoLwtTqrO/NMU/xNHNgUVScVYVXniO4teg7DjB1mcZ8 uRbpD+LkQpM/mzvVJ59Cub1kousEhmBCtYhDXveB6x1h0iQ4taFNJcoC3hQTDosg Md2kfzHsMqOnZt+wxAbj0lWcgiLmOdESEopyvAGWO2KZN8BzAojOZHpQeqejAD7x oUbu/ZZXWda3BKnTVd9hWa+2UmK7ohfcc8YowyXnceM+KDLLOd6KF2uIBHsSusPP XnZD4IgPYG/IwaTurj30wetEGHPaZmAApBGPITBFEJ747H33PaJPOl3eZXyUv0Hg /aMMVa0RcDb0WabfJlfnYD+/tGxW+sgTRZm7MvCNRVYjlKUL+7v+J0Rj79smoSNS rTeDWvVdUFAvGNMwqXJ+eGQVL1FnivUV5q1Mkt1YBEBxOHWBZHR64+kkwLp+RSkI ig2HdknVUzlZWArajxTzZkdtCR2lvZHL1lYdIiJS1tmCYwJPpGzZGlNMam4q1o70 G/5whV/xQ19xBe2VBTTmDi1vS9mxPNfnlaXrgS1HImDdQtHgv89PhTtNhEwIoAiR s+sf7mZ+OqfUTZRpEmNy =f3sy -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging # gpg: Signature made Fri 06 Nov 2015 20:01:44 GMT using RSA key ID AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" * remotes/jnsnow/tags/ide-pull-request: arm: allwinner-a10: Add SATA ahci: Add allwinner AHCI ahci: split realize and init ahci: Add some MMIO debug printfs ide: remove hardcoded 2GiB transactional limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Peter Maydell
commit
c4a7bf54e5
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@ -39,6 +39,9 @@ static void aw_a10_init(Object *obj)
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qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
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qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
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}
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static void aw_a10_realize(DeviceState *dev, Error **errp)
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@ -93,6 +96,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
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sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
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object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
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/* FIXME use a qdev chardev prop instead of serial_hds[] */
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serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
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115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
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184
hw/ide/ahci.c
184
hw/ide/ahci.c
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@ -378,17 +378,23 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
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int ofst = addr - aligned;
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uint64_t lo = ahci_mem_read_32(opaque, aligned);
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uint64_t hi;
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uint64_t val;
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/* if < 8 byte read does not cross 4 byte boundary */
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if (ofst + size <= 4) {
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return lo >> (ofst * 8);
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}
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g_assert_cmpint(size, >, 1);
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val = lo >> (ofst * 8);
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} else {
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g_assert_cmpint(size, >, 1);
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/* If the 64bit read is unaligned, we will produce undefined
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* results. AHCI does not support unaligned 64bit reads. */
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hi = ahci_mem_read_32(opaque, aligned + 4);
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return (hi << 32 | lo) >> (ofst * 8);
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/* If the 64bit read is unaligned, we will produce undefined
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* results. AHCI does not support unaligned 64bit reads. */
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hi = ahci_mem_read_32(opaque, aligned + 4);
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val = (hi << 32 | lo) >> (ofst * 8);
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}
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DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
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addr, val, size);
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return val;
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}
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@ -397,6 +403,9 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
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{
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AHCIState *s = opaque;
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DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
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addr, val, size);
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/* Only aligned reads are allowed on AHCI */
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if (addr & 3) {
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fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
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@ -804,8 +813,21 @@ static int prdt_tbl_entry_size(const AHCI_SG *tbl)
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return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
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}
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/**
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* Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
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* @ad: The AHCIDevice for whom we are building the SGList.
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* @sglist: The SGList target to add PRD entries to.
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* @cmd: The AHCI Command Header that describes where the PRDT is.
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* @limit: The remaining size of the S/ATA transaction, in bytes.
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* @offset: The number of bytes already transferred, in bytes.
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*
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* The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
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* up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
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* building the sglist from the PRDT as soon as we hit @limit bytes,
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* which is <= INT32_MAX/2GiB.
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*/
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static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
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AHCICmdHdr *cmd, int64_t limit, int32_t offset)
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AHCICmdHdr *cmd, int64_t limit, uint64_t offset)
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{
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uint16_t opts = le16_to_cpu(cmd->opts);
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uint16_t prdtl = le16_to_cpu(cmd->prdtl);
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@ -823,14 +845,6 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
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IDEBus *bus = &ad->port;
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BusState *qbus = BUS(bus);
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/*
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* Note: AHCI PRDT can describe up to 256GiB. SATA/ATA only support
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* transactions of up to 32MiB as of ATA8-ACS3 rev 1b, assuming a
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* 512 byte sector size. We limit the PRDT in this implementation to
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* a reasonably large 2GiB, which can accommodate the maximum transfer
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* request for sector sizes up to 32K.
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*/
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if (!prdtl) {
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DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
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return -1;
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@ -880,13 +894,6 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
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qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
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MIN(prdt_tbl_entry_size(&tbl[i]),
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limit - sglist->size));
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if (sglist->size > INT32_MAX) {
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error_report("AHCI Physical Region Descriptor Table describes "
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"more than 2 GiB.");
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qemu_sglist_destroy(sglist);
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r = -1;
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goto out;
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}
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}
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}
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@ -1427,7 +1434,17 @@ static const IDEDMAOps ahci_dma_ops = {
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.cmd_done = ahci_cmd_done,
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};
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void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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void ahci_init(AHCIState *s, DeviceState *qdev)
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{
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s->container = qdev;
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/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
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memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
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"ahci", AHCI_MEM_BAR_SIZE);
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memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
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"ahci-idp", 32);
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}
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void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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{
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qemu_irq *irqs;
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int i;
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@ -1435,16 +1452,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
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s->as = as;
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s->ports = ports;
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s->dev = g_new0(AHCIDevice, ports);
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s->container = qdev;
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ahci_reg_init(s);
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/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
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memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
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"ahci", AHCI_MEM_BAR_SIZE);
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memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
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"ahci-idp", 32);
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irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
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for (i = 0; i < s->ports; i++) {
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AHCIDevice *ad = &s->dev[i];
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@ -1639,17 +1648,24 @@ static void sysbus_ahci_reset(DeviceState *dev)
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ahci_reset(&s->ahci);
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}
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static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
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static void sysbus_ahci_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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SysbusAHCIState *s = SYSBUS_AHCI(dev);
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SysbusAHCIState *s = SYSBUS_AHCI(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);
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ahci_init(&s->ahci, DEVICE(obj));
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sysbus_init_mmio(sbd, &s->ahci.mem);
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sysbus_init_irq(sbd, &s->ahci.irq);
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}
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static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
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{
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SysbusAHCIState *s = SYSBUS_AHCI(dev);
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ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
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}
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static Property sysbus_ahci_properties[] = {
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DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
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DEFINE_PROP_END_OF_LIST(),
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@ -1670,12 +1686,108 @@ static const TypeInfo sysbus_ahci_info = {
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.name = TYPE_SYSBUS_AHCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SysbusAHCIState),
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.instance_init = sysbus_ahci_init,
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.class_init = sysbus_ahci_class_init,
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};
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#define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTSR ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_BISTDECR ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_DIAGNR0 ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_DIAGNR1 ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_OOBR ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS0R ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS1R ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PHYCS2R ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_TIMER1MS ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_GPARAM1R ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_GPARAM2R ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_PPARAMR ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_TESTR ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_VERSIONR ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_IDR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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#define ALLWINNER_AHCI_RWCR ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
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static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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AllwinnerAHCIState *a = opaque;
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uint64_t val = a->regs[addr/4];
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switch (addr / 4) {
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case ALLWINNER_AHCI_PHYCS0R:
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val |= 0x2 << 28;
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break;
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case ALLWINNER_AHCI_PHYCS2R:
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val &= ~(0x1 << 24);
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break;
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}
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DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
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addr, val, size);
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return val;
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}
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static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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AllwinnerAHCIState *a = opaque;
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DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
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addr, val, size);
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a->regs[addr/4] = val;
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}
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static const MemoryRegionOps allwinner_ahci_mem_ops = {
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.read = allwinner_ahci_mem_read,
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.write = allwinner_ahci_mem_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void allwinner_ahci_init(Object *obj)
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{
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SysbusAHCIState *s = SYSBUS_AHCI(obj);
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AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);
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memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,
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"allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);
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memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,
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&a->mmio);
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}
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static const VMStateDescription vmstate_allwinner_ahci = {
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.name = "allwinner-ahci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,
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ALLWINNER_AHCI_MMIO_SIZE/4),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_ahci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_allwinner_ahci;
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}
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static const TypeInfo allwinner_ahci_info = {
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.name = TYPE_ALLWINNER_AHCI,
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.parent = TYPE_SYSBUS_AHCI,
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.instance_size = sizeof(AllwinnerAHCIState),
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.instance_init = allwinner_ahci_init,
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.class_init = allwinner_ahci_class_init,
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};
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static void sysbus_ahci_register_types(void)
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{
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type_register_static(&sysbus_ahci_info);
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type_register_static(&allwinner_ahci_info);
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}
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|
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type_init(sysbus_ahci_register_types)
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|
|
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|||
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@ -366,7 +366,8 @@ typedef struct SDBFIS {
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|||
uint32_t payload;
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} QEMU_PACKED SDBFIS;
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|
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void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
|
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void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
|
||||
void ahci_init(AHCIState *s, DeviceState *qdev);
|
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void ahci_uninit(AHCIState *s);
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||||
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||||
void ahci_reset(AHCIState *s);
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||||
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@ -385,4 +386,20 @@ typedef struct SysbusAHCIState {
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uint32_t num_ports;
|
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} SysbusAHCIState;
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||||
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||||
#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
|
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#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \
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TYPE_ALLWINNER_AHCI)
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||||
|
||||
#define ALLWINNER_AHCI_MMIO_OFF 0x80
|
||||
#define ALLWINNER_AHCI_MMIO_SIZE 0x80
|
||||
|
||||
struct AllwinnerAHCIState {
|
||||
/*< private >*/
|
||||
SysbusAHCIState parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
MemoryRegion mmio;
|
||||
uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
|
||||
};
|
||||
|
||||
#endif /* HW_IDE_AHCI_H */
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||||
|
|
|
|||
10
hw/ide/ich.c
10
hw/ide/ich.c
|
|
@ -97,6 +97,13 @@ static void pci_ich9_reset(DeviceState *dev)
|
|||
ahci_reset(&d->ahci);
|
||||
}
|
||||
|
||||
static void pci_ich9_ahci_init(Object *obj)
|
||||
{
|
||||
struct AHCIPCIState *d = ICH_AHCI(obj);
|
||||
|
||||
ahci_init(&d->ahci, DEVICE(obj));
|
||||
}
|
||||
|
||||
static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
|
||||
{
|
||||
struct AHCIPCIState *d;
|
||||
|
|
@ -104,7 +111,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
|
|||
uint8_t *sata_cap;
|
||||
d = ICH_AHCI(dev);
|
||||
|
||||
ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
|
||||
ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
|
||||
|
||||
pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
|
||||
|
||||
|
|
@ -171,6 +178,7 @@ static const TypeInfo ich_ahci_info = {
|
|||
.name = TYPE_ICH9_AHCI,
|
||||
.parent = TYPE_PCI_DEVICE,
|
||||
.instance_size = sizeof(AHCIPCIState),
|
||||
.instance_init = pci_ich9_ahci_init,
|
||||
.class_init = ich_ahci_class_init,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@ struct IDEState {
|
|||
struct iovec iov;
|
||||
QEMUIOVector qiov;
|
||||
/* ATA DMA state */
|
||||
int32_t io_buffer_offset;
|
||||
uint64_t io_buffer_offset;
|
||||
int32_t io_buffer_size;
|
||||
QEMUSGList sg;
|
||||
/* PIO transfer handling */
|
||||
|
|
|
|||
|
|
@ -103,13 +103,6 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
|
|||
qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
|
||||
}
|
||||
|
||||
/* Note: We limit the max transfer to be 2GiB.
|
||||
* This should accommodate the largest ATA transaction
|
||||
* for LBA48 (65,536 sectors) and 32K sector sizes. */
|
||||
if (s->sg.size > INT32_MAX) {
|
||||
error_report("IDE: sglist describes more than 2GiB.");
|
||||
break;
|
||||
}
|
||||
bm->cur_prd_addr += l;
|
||||
bm->cur_prd_len -= l;
|
||||
s->io_buffer_size += l;
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
#include "hw/timer/allwinner-a10-pit.h"
|
||||
#include "hw/intc/allwinner-a10-pic.h"
|
||||
#include "hw/net/allwinner_emac.h"
|
||||
#include "hw/ide/pci.h"
|
||||
#include "hw/ide/ahci.h"
|
||||
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "exec/address-spaces.h"
|
||||
|
|
@ -16,6 +18,7 @@
|
|||
#define AW_A10_PIT_REG_BASE 0x01c20c00
|
||||
#define AW_A10_UART0_REG_BASE 0x01c28000
|
||||
#define AW_A10_EMAC_BASE 0x01c0b000
|
||||
#define AW_A10_SATA_BASE 0x01c18000
|
||||
|
||||
#define AW_A10_SDRAM_BASE 0x40000000
|
||||
|
||||
|
|
@ -32,6 +35,7 @@ typedef struct AwA10State {
|
|||
AwA10PITState timer;
|
||||
AwA10PICState intc;
|
||||
AwEmacState emac;
|
||||
AllwinnerAHCIState sata;
|
||||
} AwA10State;
|
||||
|
||||
#define ALLWINNER_H_
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ struct Monitor;
|
|||
typedef struct AdapterInfo AdapterInfo;
|
||||
typedef struct AddressSpace AddressSpace;
|
||||
typedef struct AioContext AioContext;
|
||||
typedef struct AllwinnerAHCIState AllwinnerAHCIState;
|
||||
typedef struct AudioState AudioState;
|
||||
typedef struct BlockBackend BlockBackend;
|
||||
typedef struct BlockBackendRootState BlockBackendRootState;
|
||||
|
|
|
|||
Loading…
Reference in New Issue