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hw/intc/arm_gicv3: Report the VINMI interrupt 

In vCPU Interface, if the vIRQ has the non-maskable property, report
vINMI to the corresponding vPE.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Jinjie Ruan 2024-04-19 14:33:05 +01:00 committed by Peter Maydell
parent f3c26a44fe
commit c57e81889f
1 changed files with 12 additions and 2 deletions
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14
hw/intc/arm_gicv3_cpuif.c
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@ -481,6 +481,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
int idx;
int irqlevel = 0;
int fiqlevel = 0;
int nmilevel = 0;
idx = hppvi_index(cs);
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx,
@ -498,9 +499,17 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
uint64_t lr = cs->ich_lr_el2[idx];
if (icv_hppi_can_preempt(cs, lr)) {
/* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
/*
* Virtual interrupts are simple: G0 are always FIQ, and G1 are
* IRQ or NMI which depends on the ICH_LR<n>_EL2.NMI to have
* non-maskable property.
*/
if (lr & ICH_LR_EL2_GROUP) {
irqlevel = 1;
if (lr & ICH_LR_EL2_NMI) {
nmilevel = 1;
} else {
irqlevel = 1;
}
} else {
fiqlevel = 1;
}
@ -510,6 +519,7 @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
qemu_set_irq(cs->parent_vfiq, fiqlevel);
qemu_set_irq(cs->parent_virq, irqlevel);
qemu_set_irq(cs->parent_vnmi, nmilevel);
}
static void gicv3_cpuif_virt_update(GICv3CPUState *cs)