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Convert target/sparc to decodetree. 

-----BEGIN PGP SIGNATURE-----
 
 iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5ruAdHHJpY2hhcmQu
 aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9NWQgAjkWxZi9Je3yWR0x0
 mQmlx0zlyjK4PeMGS14mr0mxFAqvC5gFHNzw0WtLaVw9gyfm6EKXwervtm9mCg7F
 PPQzF9IqSoKqGV2fFlWpVWmUPmKNhLY5hS7Pvampg8Tkt6X6NJQdbaUpEQW6U47I
 C4/AAygaj6fd99BEZI36A2oxg6D0HM9cV1LUm43e+yQ1KCQaTO+3u8oDZA8MkXu1
 p2bxPXazClLe+ywwtR9tp28IgQszQ10NxECzhJ34ezLCbTreH//ycpPI2h8Xskdc
 lDkCu3OJa8aIalGOpDL71Qemp9KfRYkOyPlahAZx3haZC24fnVvVRoMiV8Z5+iYk
 gq2VnA==
 =/gf2
 -----END PGP SIGNATURE-----

Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging

Convert target/sparc to decodetree.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5ruAdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9NWQgAjkWxZi9Je3yWR0x0
# mQmlx0zlyjK4PeMGS14mr0mxFAqvC5gFHNzw0WtLaVw9gyfm6EKXwervtm9mCg7F
# PPQzF9IqSoKqGV2fFlWpVWmUPmKNhLY5hS7Pvampg8Tkt6X6NJQdbaUpEQW6U47I
# C4/AAygaj6fd99BEZI36A2oxg6D0HM9cV1LUm43e+yQ1KCQaTO+3u8oDZA8MkXu1
# p2bxPXazClLe+ywwtR9tp28IgQszQ10NxECzhJ34ezLCbTreH//ycpPI2h8Xskdc
# lDkCu3OJa8aIalGOpDL71Qemp9KfRYkOyPlahAZx3haZC24fnVvVRoMiV8Z5+iYk
# gq2VnA==
# =/gf2
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 26 Oct 2023 09:12:16 JST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu: (94 commits)
  target/sparc: Remove disas_sparc_legacy
  target/sparc: Convert FZERO, FONE to decodetree
  target/sparc: Move FPACK16, FPACKFIX to decodetree
  target/sparc: Move FPCMP* to decodetree
  target/sparc: Convert FCMP, FCMPE to decodetree
  target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
  target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
  target/sparc: Move FdTOq, FxTOq to decodetree
  target/sparc: Move FiTOq, FsTOq to decodetree
  target/sparc: Move FqTOd, FqTOx to decodetree
  target/sparc: Move FqTOs, FqTOi to decodetree
  target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
  target/sparc: Move gen_fop_FD insns to decodetree
  target/sparc: Move FDMULQ to decodetree
  target/sparc: Move FSMULD to decodetree
  target/sparc: Move gen_fop_QQQ insns to decodetree
  target/sparc: Move gen_fop_DDD insns to decodetree
  target/sparc: Move gen_fop_FFF insns to decodetree
  target/sparc: Move FSQRTq to decodetree
  target/sparc: Move gen_fop_DD insns to decodetree
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
master
Stefan Hajnoczi 2023-10-27 09:43:53 +09:00
parent 3c95fd4ed8 ba9c09b40b
commit c60be6e3e3
14 changed files with 4028 additions and 3780 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
configs/targets/sparc-softmmu.mak
View File

@ -1,2 +1,3 @@
TARGET_ARCH=sparc
TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y

1
configs/targets/sparc64-softmmu.mak
View File

@ -1,3 +1,4 @@
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_BIG_ENDIAN=y
TARGET_SUPPORTS_MTTCG=y

6
linux-user/sparc/target_syscall.h
View File

@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env)
#ifdef TARGET_SPARC64
return MAX(TARGET_PAGE_SIZE, 16 * 1024);
#else
if (!(env->def.features & CPU_FEATURE_FLUSH)) {
return 64 * 1024;
} else {
return 256 * 1024;
}
return 256 * 1024;
#endif
}

14
target/sparc/cpu-feature.h.inc Normal file
View File

@ -0,0 +1,14 @@
FEATURE(FLOAT128)
FEATURE(MUL)
FEATURE(DIV)
FEATURE(VIS1)
FEATURE(VIS2)
FEATURE(FSMULD)
FEATURE(HYPV)
FEATURE(CMT)
FEATURE(GL)
FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */
FEATURE(ASR17)
FEATURE(CACHE_CTRL)
FEATURE(POWERDOWN)
FEATURE(CASA)

72
target/sparc/cpu.c
View File

@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] = {
.mmu_sfsr_mask = 0x00016fff,
.mmu_trcr_mask = 0x0000003f,
.nwindows = 7,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
CPU_FEATURE_FMUL,
.features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
},
{
.name = "TI MicroSparc II",
@ -545,21 +543,20 @@ static const sparc_def_t sparc_defs[] = {
#endif
};
/* This must match sparc_cpu_properties[]. */
static const char * const feature_name[] = {
"float",
"float128",
"swap",
"mul",
"div",
"flush",
"fsqrt",
"fmul",
"vis1",
"vis2",
"fsmuld",
"hypv",
"cmt",
"gl",
[CPU_FEATURE_BIT_FLOAT128] = "float128",
#ifdef TARGET_SPARC64
[CPU_FEATURE_BIT_CMT] = "cmt",
[CPU_FEATURE_BIT_GL] = "gl",
[CPU_FEATURE_BIT_HYPV] = "hypv",
[CPU_FEATURE_BIT_VIS1] = "vis1",
[CPU_FEATURE_BIT_VIS2] = "vis2",
#else
[CPU_FEATURE_BIT_MUL] = "mul",
[CPU_FEATURE_BIT_DIV] = "div",
[CPU_FEATURE_BIT_FSMULD] = "fsmuld",
#endif
};
static void print_features(uint32_t features, const char *prefix)
@ -757,9 +754,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
CPUSPARCState *env = &cpu->env;
#if defined(CONFIG_USER_ONLY)
if ((env->def.features & CPU_FEATURE_FLOAT)) {
env->def.features |= CPU_FEATURE_FLOAT128;
}
/* We are emulating the kernel, which will trap and emulate float128. */
env->def.features |= CPU_FEATURE_FLOAT128;
#endif
env->version = env->def.iu_version;
@ -835,21 +831,29 @@ static PropertyInfo qdev_prop_nwindows = {
.set = sparc_set_nwindows,
};
/* This must match feature_name[]. */
static Property sparc_cpu_properties[] = {
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FLOAT128, false),
#ifdef TARGET_SPARC64
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_CMT, false),
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_GL, false),
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_HYPV, false),
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS1, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS2, false),
#else
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_MUL, false),
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_DIV, false),
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FSMULD, false),
#endif
DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
qdev_prop_uint64, target_ulong),
DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),

76
target/sparc/cpu.h
View File

@ -6,6 +6,29 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
/*
* From Oracle SPARC Architecture 2015:
*
* Compatibility notes: The PSO memory model described in SPARC V8 and
* SPARC V9 compatibility architecture specifications was never implemented
* in a SPARC V9 implementation and is not included in the Oracle SPARC
* Architecture specification.
*
* The RMO memory model described in the SPARC V9 specification was
* implemented in some non-Sun SPARC V9 implementations, but is not
* directly supported in Oracle SPARC Architecture 2015 implementations.
*
* Therefore always use TSO in QEMU.
*
* D.5 Specification of Partial Store Order (PSO)
* ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
*
* D.6 Specification of Total Store Order (TSO)
* ... PSO with the additional requirement that all [stores] are followed
* by an implied MEMBAR #StoreStore.
*/
#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
#else
@ -268,38 +291,27 @@ struct sparc_def_t {
uint32_t maxtl;
};
#define CPU_FEATURE_FLOAT (1 << 0)
#define CPU_FEATURE_FLOAT128 (1 << 1)
#define CPU_FEATURE_SWAP (1 << 2)
#define CPU_FEATURE_MUL (1 << 3)
#define CPU_FEATURE_DIV (1 << 4)
#define CPU_FEATURE_FLUSH (1 << 5)
#define CPU_FEATURE_FSQRT (1 << 6)
#define CPU_FEATURE_FMUL (1 << 7)
#define CPU_FEATURE_VIS1 (1 << 8)
#define CPU_FEATURE_VIS2 (1 << 9)
#define CPU_FEATURE_FSMULD (1 << 10)
#define CPU_FEATURE_HYPV (1 << 11)
#define CPU_FEATURE_CMT (1 << 12)
#define CPU_FEATURE_GL (1 << 13)
#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
#define CPU_FEATURE_ASR17 (1 << 15)
#define CPU_FEATURE_CACHE_CTRL (1 << 16)
#define CPU_FEATURE_POWERDOWN (1 << 17)
#define CPU_FEATURE_CASA (1 << 18)
#define FEATURE(X) CPU_FEATURE_BIT_##X,
enum {
#include "cpu-feature.h.inc"
};
#undef FEATURE
#define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X,
enum {
#include "cpu-feature.h.inc"
};
#undef FEATURE
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD)
#else
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
CPU_FEATURE_CASA)
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \
CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2)
enum {
mmu_us_12, // Ultrasparc < III (64 entry TLB)
mmu_us_3, // Ultrasparc III (512 entry TLB)
@ -782,14 +794,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
if (env->pstate & PS_AM) {
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def.features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
if (env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
}
#endif

17
target/sparc/fop_helper.c
View File

@ -382,20 +382,7 @@ static void set_fsr(CPUSPARCState *env, target_ulong fsr)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
uint32_t new_fsr)
void helper_set_fsr(CPUSPARCState *env, target_ulong fsr)
{
old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
set_fsr(env, fsr);
}
#ifdef TARGET_SPARC64
target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
uint64_t new_fsr)
{
old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#endif

8
target/sparc/helper.c
View File

@ -102,9 +102,7 @@ static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}
@ -143,9 +141,7 @@ static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a,
}
if (cc) {
env->cc_dst = x0;
env->cc_src2 = overflow;
env->cc_op = CC_OP_DIV;
}
return x0;
}
@ -202,10 +198,8 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TADDTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;
tag_overflow:
@ -230,10 +224,8 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
}
/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TSUBTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;
tag_overflow:

16
target/sparc/helper.h
View File

@ -24,7 +24,6 @@ DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void, ptr, i64)
DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int)
DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
#endif
DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
DEF_HELPER_1(restore, void, env)
@ -43,7 +42,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
@ -55,7 +54,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64)
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
@ -139,18 +137,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
#define VIS_HELPER(name) \
DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \
i32, i32, i32) \
DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \
i32, i32, i32)
VIS_HELPER(padd)
VIS_HELPER(psub)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \

547
target/sparc/insns.decode Normal file
View File

@ -0,0 +1,547 @@
# SPDX-License-Identifier: LGPL-2.0+
#
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
##
## Major Opcodes 00 and 01 -- branches, call, and sethi.
##
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
NCP 00 - ---- 111 ---------------------- # CBcc
SETHI 00 rd:5 100 i:22
CALL 01 i:s30
##
## Major Opcode 10 -- integer, floating-point, vis, and system insns.
##
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
&r_r_r rd rs1 rs2
@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
@r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r
&r_r rd rs
@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r
@r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r
{
[
STBAR 10 00000 101000 01111 0 0000000000000
MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
RDCCR 10 rd:5 101000 00010 0 0000000000000
RDASI 10 rd:5 101000 00011 0 0000000000000
RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000
RDASR17 10 rd:5 101000 10001 0 0000000000000
RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
RDSTICK 10 rd:5 101000 11000 0 0000000000000
RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
]
# Before v8, all rs1 accepted; otherwise rs1==0.
RDY 10 rd:5 101000 rs1:5 0 0000000000000
}
{
[
WRY 10 00000 110000 ..... . ............. @n_r_ri
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
{
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
}
WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri
WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri
WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri
WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
]
# Before v8, rs1==0 was WRY, and the rest executed as nop.
[
NOP_v7 10 ----- 110000 ----- 0 00000000 -----
NOP_v7 10 ----- 110000 ----- 1 -------- -----
]
}
{
RDPSR 10 rd:5 101001 00000 0 0000000000000
RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
}
RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
{
WRPSR 10 00000 110001 ..... . ............. @n_r_ri
SAVED 10 00000 110001 00000 0 0000000000000
}
RESTORED 10 00001 110001 00000 0 0000000000000
# UA2005 ALLCLEAN
# UA2005 OTHERW
# UA2005 NORMALW
# UA2005 INVALW
{
RDWIM 10 rd:5 101010 00000 0 0000000000000
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
}
RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
RDPR_tt 10 rd:5 101010 00011 0 0000000000000
RDPR_tick 10 rd:5 101010 00100 0 0000000000000
RDPR_tba 10 rd:5 101010 00101 0 0000000000000
RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
RDPR_tl 10 rd:5 101010 00111 0 0000000000000
RDPR_pil 10 rd:5 101010 01000 0 0000000000000
RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
{
WRWIM 10 00000 110010 ..... . ............. @n_r_ri
WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri
}
WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri
WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri
WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri
WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri
WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri
WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri
WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri
WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri
WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri
WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri
WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri
WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri
WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri
WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri
WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri
WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri
{
FLUSHW 10 00000 101011 00000 0 0000000000000
RDTBR 10 rd:5 101011 00000 0 0000000000000
}
{
WRTBR 10 00000 110011 ..... . ............. @n_r_ri
WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
}
WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri
WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc
AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc
OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc
XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc
ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1
POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \
&r_r_ri_cc rs1=0 cc=0
&shiftr rd rs1 rs2 x:bool
@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr
SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr
SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr
SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr
&shifti rd rs1 i x:bool
@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti
SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti
SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti
SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
# For v8, [12:7] are reserved. However, a compatibility note for
# the Tcc insn in the v9 manual suggests that the v8 reserved field
# was ignored and did not produce traps.
Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
}
MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11
MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10
JMPL 10 ..... 111000 ..... . ............. @r_r_ri
{
RETT 10 00000 111001 ..... . ............. @n_r_ri
RETURN 10 00000 111001 ..... . ............. @n_r_ri
}
NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg
NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm
SAVE 10 ..... 111100 ..... . ............. @r_r_ri
RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2
FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2
FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2
FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r
FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r
FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r
FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r
FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r
FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r
FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r
FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r
FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r
FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2
FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2
FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2
FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2
FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2
FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2
FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2
FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2
FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2
FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2
FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2
FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5
FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5
FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5
FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5
FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5
FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5
FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5
FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5
FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5
FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5
FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5
FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5
FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5
FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5
FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r
EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r
EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r
EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r
EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r
EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r
EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r
EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r
EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r
EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r
EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r
ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r
ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r
ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r
FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r
FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r
FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r
FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r
FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r
FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r
FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r
FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r
FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r
FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r
FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2
FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2
PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r
FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d
FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s
FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d
FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d
FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r
FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r
FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r
FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r
FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r
FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r
FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r
FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r
FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r
FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FANDNOT2d
FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s
FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # ... 1d
FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s
FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r
FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r
FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r
FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r
FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r
FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r
FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r
FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r
FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FORNOT2d
FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s
FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # ... 1d
FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s
FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r
FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r
FZEROd 10 rd:5 110110 00000 0 0110 0000 00000
FZEROs 10 rd:5 110110 00000 0 0110 0001 00000
FONEd 10 rd:5 110110 00000 0 0111 1110 00000
FONEs 10 rd:5 110110 00000 0 0111 1111 00000
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
##
## Major Opcode 11 -- load and store instructions
##
%dfp_rd 25:5 !function=extract_dfpreg
%qfp_rd 25:5 !function=extract_qfpreg
&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool
@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1
@d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \
&r_r_ri_asi rd=%dfp_rd asi=-1
@q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \
&r_r_ri_asi rd=%qfp_rd asi=-1
@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0
@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \
&r_r_ri_asi imm=1 asi=-2
@d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
&r_r_ri_asi rd=%dfp_rd imm=0
@d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
&r_r_ri_asi rd=%dfp_rd imm=1 asi=-2
@q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
&r_r_ri_asi rd=%qfp_rd imm=0
@q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
&r_r_ri_asi rd=%qfp_rd imm=1 asi=-2
@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \
&r_r_ri_asi imm=1 asi=-2
LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na
LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na
LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na
LDD 11 ..... 000011 ..... . ............. @r_r_ri_na
LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na
LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na
LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na
LDX 11 ..... 001011 ..... . ............. @r_r_ri_na
STW 11 ..... 000100 ..... . ............. @r_r_ri_na
STB 11 ..... 000101 ..... . ............. @r_r_ri_na
STH 11 ..... 000110 ..... . ............. @r_r_ri_na
STD 11 ..... 000111 ..... . ............. @r_r_ri_na
STX 11 ..... 001110 ..... . ............. @r_r_ri_na
LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA
LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA
LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA
LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA
LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA
LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA
LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA
LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA
LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA
LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA
LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA
LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA
LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA
LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA
LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA
LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA
STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA
STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA
STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA
STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA
STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA
STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA
STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA
STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA
STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA
STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA
LDF 11 ..... 100000 ..... . ............. @r_r_ri_na
LDFSR 11 00000 100001 ..... . ............. @n_r_ri
LDXFSR 11 00001 100001 ..... . ............. @n_r_ri
LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na
LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na
STF 11 ..... 100100 ..... . ............. @r_r_ri_na
STFSR 11 00000 100101 ..... . ............. @n_r_ri
STXFSR 11 00001 100101 ..... . ............. @n_r_ri
{
STQF 11 ..... 100110 ..... . ............. @q_r_ri_na
STDFQ 11 ----- 100110 ----- - -------------
}
STDF 11 ..... 100111 ..... . ............. @d_r_ri_na
LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na
LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA
LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA
SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na
SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA
SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA
CASA 11 ..... 111100 ..... . ............. @r_r_r_asi
CASA 11 ..... 111100 ..... . ............. @casa_imm
CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
CASXA 11 ..... 111110 ..... . ............. @casa_imm
NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
{
[
LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi
LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi
]
NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
}
NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi
LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi
{
[
LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi
LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi
]
NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC
}
{
[
STFA 11 ..... 110100 ..... . ............. @r_r_r_asi
STFA 11 ..... 110100 ..... . ............. @r_r_i_asi
]
NCP 11 ----- 110100 ----- --------- ----- # v8 STC
}
NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR
{
[
STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi
STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi
]
NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ
}
{
[
STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi
STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi
]
NCP 11 ----- 110111 ----- --------- ----- # v8 STDC
}

17
target/sparc/ldst_helper.c
View File

@ -360,6 +360,7 @@ static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
#endif /* !CONFIG_USER_ONLY */
#endif
#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
static void do_check_align(CPUSPARCState *env, target_ulong addr,
uint32_t align, uintptr_t ra)
{
@ -367,11 +368,7 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr,
cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
}
}
void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
{
do_check_align(env, addr, align, GETPC());
}
#endif
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
defined(DEBUG_MXCC)
@ -1653,7 +1650,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->dmmu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x33:
@ -1665,7 +1662,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
*/
env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x35:
@ -1682,7 +1679,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
env->immu.sun4v_tsb_pointers[idx] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case 0x37:
@ -1694,7 +1691,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
*/
env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
} else {
helper_raise_exception(env, TT_ILL_INSN);
goto illegal_insn;
}
break;
case ASI_UPA_CONFIG: /* UPA config */
@ -1923,6 +1920,8 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
default:
sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
return;
illegal_insn:
cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
}
}
#endif /* CONFIG_USER_ONLY */

3
target/sparc/meson.build
View File

@ -1,4 +1,7 @@
gen = decodetree.process('insns.decode')
sparc_ss = ss.source_set()
sparc_ss.add(gen)
sparc_ss.add(files(
'cc_helper.c',
'cpu.c',

6971
target/sparc/translate.c
View File

File diff suppressed because it is too large Load Diff

59
target/sparc/vis_helper.c
View File

@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
return d.ll;
}
#define VIS_HELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
\
return d.ll; \
} \
\
uint32_t name##16s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
s.l = src1; \
d.l = src2; \
\
d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
\
return d.l; \
} \
\
uint64_t name##32(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
\
return d.ll; \
} \
\
uint32_t name##32s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
s.l = src1; \
d.l = src2; \
\
d.l = F(d.l, s.l); \
\
return d.l; \
}
#define FADD(a, b) ((a) + (b))
#define FSUB(a, b) ((a) - (b))
VIS_HELPER(helper_fpadd, FADD)
VIS_HELPER(helper_fpsub, FSUB)
#define VIS_CMPHELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \