mirror of https://github.com/proxmox/mirror_qemu
Collapse omap peripherals on L4 bus into one io entry (temporarily).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4489 c046a42c-6fe2-441c-8c8c-71466251a162master
parent
4eeed608c5
commit
c66fb5bc0a
10
hw/omap.h
10
hw/omap.h
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@ -71,6 +71,7 @@ struct omap_target_agent_s;
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struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
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struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
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target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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int iotype);
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int iotype);
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# define l4_register_io_memory cpu_register_io_memory
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struct omap_intr_handler_s;
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struct omap_intr_handler_s;
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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@ -1135,4 +1136,13 @@ inline static int debug_register_io_memory(int io_index,
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# define cpu_register_io_memory debug_register_io_memory
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# define cpu_register_io_memory debug_register_io_memory
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# endif
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# endif
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/* Define when we want to reduce the number of IO regions registered. */
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# define L4_MUX_HACK
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# ifdef L4_MUX_HACK
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# undef l4_register_io_memory
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int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write, void *opaque);
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# endif
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#endif /* hw_omap_h */
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#endif /* hw_omap_h */
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146
hw/omap2.c
146
hw/omap2.c
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@ -485,7 +485,7 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
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omap_gp_timer_reset(s);
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omap_gp_timer_reset(s);
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omap_gp_timer_clk_setup(s);
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omap_gp_timer_clk_setup(s);
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iomemtype = cpu_register_io_memory(0, omap_gp_timer_readfn,
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iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
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omap_gp_timer_writefn, s);
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omap_gp_timer_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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@ -557,7 +557,7 @@ void omap_synctimer_init(struct omap_target_agent_s *ta,
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struct omap_synctimer_s *s = &mpu->synctimer;
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struct omap_synctimer_s *s = &mpu->synctimer;
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omap_synctimer_reset(s);
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omap_synctimer_reset(s);
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s->base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
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s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
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omap_synctimer_readfn, omap_synctimer_writefn, s));
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omap_synctimer_readfn, omap_synctimer_writefn, s));
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}
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}
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@ -960,7 +960,7 @@ static void omap_gpio_module_init(struct omap2_gpio_s *s,
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s->wkup = wkup;
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s->wkup = wkup;
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s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
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s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
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iomemtype = cpu_register_io_memory(0, omap_gpio_module_readfn,
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iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
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omap_gpio_module_writefn, s);
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omap_gpio_module_writefn, s);
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s->base = omap_l4_attach(ta, region, iomemtype);
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s->base = omap_l4_attach(ta, region, iomemtype);
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}
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}
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@ -1071,7 +1071,7 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
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omap_gpif_reset(s);
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omap_gpif_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_gpif_top_readfn,
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iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
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omap_gpif_top_writefn, s);
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omap_gpif_top_writefn, s);
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s->topbase = omap_l4_attach(ta, 1, iomemtype);
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s->topbase = omap_l4_attach(ta, 1, iomemtype);
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@ -1401,7 +1401,7 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
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}
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}
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omap_mcspi_reset(s);
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omap_mcspi_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_mcspi_readfn,
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iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
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omap_mcspi_writefn, s);
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omap_mcspi_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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@ -1602,7 +1602,7 @@ struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
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s->chr = chr ?: qemu_chr_open("null");
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s->chr = chr ?: qemu_chr_open("null");
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iomemtype = cpu_register_io_memory(0, omap_sti_readfn,
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iomemtype = l4_register_io_memory(0, omap_sti_readfn,
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omap_sti_writefn, s);
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omap_sti_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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@ -1631,6 +1631,90 @@ struct omap_l4_s {
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struct omap_target_agent_s ta[0];
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struct omap_target_agent_s ta[0];
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};
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};
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#ifdef L4_MUX_HACK
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static int omap_l4_io_entries;
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static int omap_cpu_io_entry;
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static struct omap_l4_entry {
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CPUReadMemoryFunc **mem_read;
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CPUWriteMemoryFunc **mem_write;
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void *opaque;
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} *omap_l4_io_entry;
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static CPUReadMemoryFunc **omap_l4_io_readb_fn;
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static CPUReadMemoryFunc **omap_l4_io_readh_fn;
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static CPUReadMemoryFunc **omap_l4_io_readw_fn;
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static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
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static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
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static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
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static void **omap_l4_io_opaque;
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int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write, void *opaque)
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{
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omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
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omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
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omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
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return omap_l4_io_entries ++;
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}
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static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
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}
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static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
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}
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static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
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}
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static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
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return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
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}
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static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
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omap_l4_io_readb,
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omap_l4_io_readh,
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omap_l4_io_readw,
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};
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static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
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omap_l4_io_writeb,
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omap_l4_io_writeh,
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omap_l4_io_writew,
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};
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#endif
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struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
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struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
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{
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{
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struct omap_l4_s *bus = qemu_mallocz(
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struct omap_l4_s *bus = qemu_mallocz(
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@ -1639,6 +1723,23 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
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bus->ta_num = ta_num;
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bus->ta_num = ta_num;
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bus->base = base;
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bus->base = base;
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#ifdef L4_MUX_HACK
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omap_l4_io_entries = 1;
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omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
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omap_cpu_io_entry =
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cpu_register_io_memory(0, omap_l4_io_readfn,
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omap_l4_io_writefn, bus);
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# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
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omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
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omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
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#endif
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return bus;
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return bus;
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}
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}
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@ -1917,15 +2018,14 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
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ta->bus = bus;
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ta->bus = bus;
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ta->start = &omap_l4_region[info->region];
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ta->start = &omap_l4_region[info->region];
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ta->regions = info->regions;
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ta->regions = info->regions;
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ta->base = bus->base + ta->start[info->ta_region].offset;
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ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
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ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
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ta->status = 0x00000000;
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ta->status = 0x00000000;
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ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
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ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
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iomemtype = cpu_register_io_memory(0, omap_l4ta_readfn,
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iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
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omap_l4ta_writefn, ta);
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omap_l4ta_writefn, ta);
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cpu_register_physical_memory(ta->base, 0x200, iomemtype);
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ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
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return ta;
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return ta;
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}
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}
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@ -1934,7 +2034,10 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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int iotype)
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int iotype)
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{
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{
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target_phys_addr_t base;
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target_phys_addr_t base;
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size_t size;
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ssize_t size;
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#ifdef L4_MUX_HACK
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int i;
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#endif
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if (region < 0 || region >= ta->regions) {
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if (region < 0 || region >= ta->regions) {
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fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
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fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
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@ -1943,8 +2046,23 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
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base = ta->bus->base + ta->start[region].offset;
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base = ta->bus->base + ta->start[region].offset;
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size = ta->start[region].size;
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size = ta->start[region].size;
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if (iotype)
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if (iotype) {
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#ifndef L4_MUX_HACK
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cpu_register_physical_memory(base, size, iotype);
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cpu_register_physical_memory(base, size, iotype);
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#else
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cpu_register_physical_memory(base, size, omap_cpu_io_entry);
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i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
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for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
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omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
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omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
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omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
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omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
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omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
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omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
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omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
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}
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#endif
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}
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return base;
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return base;
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}
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}
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@ -2036,7 +2154,7 @@ static CPUWriteMemoryFunc *omap_tap_writefn[] = {
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void omap_tap_init(struct omap_target_agent_s *ta,
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void omap_tap_init(struct omap_target_agent_s *ta,
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struct omap_mpu_state_s *mpu)
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struct omap_mpu_state_s *mpu)
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{
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{
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mpu->tap_base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
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mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
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omap_tap_readfn, omap_tap_writefn, mpu));
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omap_tap_readfn, omap_tap_writefn, mpu));
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}
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}
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@ -2755,7 +2873,7 @@ struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
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s->mpu = mpu;
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s->mpu = mpu;
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omap_prcm_coldreset(s);
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omap_prcm_coldreset(s);
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iomemtype = cpu_register_io_memory(0, omap_prcm_readfn,
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iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
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omap_prcm_writefn, s);
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omap_prcm_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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omap_l4_attach(ta, 1, iomemtype);
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omap_l4_attach(ta, 1, iomemtype);
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@ -3079,7 +3197,7 @@ struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
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s->mpu = mpu;
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s->mpu = mpu;
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omap_sysctl_reset(s);
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omap_sysctl_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_sysctl_readfn,
|
iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
|
||||||
omap_sysctl_writefn, s);
|
omap_sysctl_writefn, s);
|
||||||
s->base = omap_l4_attach(ta, 0, iomemtype);
|
s->base = omap_l4_attach(ta, 0, iomemtype);
|
||||||
omap_l4_attach(ta, 0, iomemtype);
|
omap_l4_attach(ta, 0, iomemtype);
|
||||||
|
|
|
@ -1059,13 +1059,13 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
|
||||||
s->state = ds;
|
s->state = ds;
|
||||||
omap_dss_reset(s);
|
omap_dss_reset(s);
|
||||||
|
|
||||||
iomemtype[0] = cpu_register_io_memory(0, omap_diss1_readfn,
|
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
|
||||||
omap_diss1_writefn, s);
|
omap_diss1_writefn, s);
|
||||||
iomemtype[1] = cpu_register_io_memory(0, omap_disc1_readfn,
|
iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn,
|
||||||
omap_disc1_writefn, s);
|
omap_disc1_writefn, s);
|
||||||
iomemtype[2] = cpu_register_io_memory(0, omap_rfbi1_readfn,
|
iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn,
|
||||||
omap_rfbi1_writefn, s);
|
omap_rfbi1_writefn, s);
|
||||||
iomemtype[3] = cpu_register_io_memory(0, omap_venc1_readfn,
|
iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn,
|
||||||
omap_venc1_writefn, s);
|
omap_venc1_writefn, s);
|
||||||
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
|
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
|
||||||
omap_im3_writefn, s);
|
omap_im3_writefn, s);
|
||||||
|
|
|
@ -526,7 +526,7 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
|
||||||
s->bus = i2c_init_bus();
|
s->bus = i2c_init_bus();
|
||||||
omap_i2c_reset(s);
|
omap_i2c_reset(s);
|
||||||
|
|
||||||
iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
|
iomemtype = l4_register_io_memory(0, omap_i2c_readfn,
|
||||||
omap_i2c_writefn, s);
|
omap_i2c_writefn, s);
|
||||||
s->base = omap_l4_attach(ta, 0, iomemtype);
|
s->base = omap_l4_attach(ta, 0, iomemtype);
|
||||||
|
|
||||||
|
|
|
@ -615,7 +615,7 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
|
||||||
|
|
||||||
omap_mmc_reset(s);
|
omap_mmc_reset(s);
|
||||||
|
|
||||||
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
|
iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
|
||||||
omap_mmc_writefn, s);
|
omap_mmc_writefn, s);
|
||||||
s->base = omap_l4_attach(ta, 0, iomemtype);
|
s->base = omap_l4_attach(ta, 0, iomemtype);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue