vitalif
/
mirror_qemu
mirror of https://github.com/proxmox/mirror_qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

hw/intc/arm_gicv3_its: Implement VINVALL 

The VINVALL command should cause any cached information in the
ITS or redistributor for the specified vCPU to be dropped or
otherwise made consistent with the in-memory LPI configuration
tables.

Here we implement the command and table parsing, leaving the
redistributor part as a stub for the moment, as usual.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-22-peter.maydell@linaro.org
master
Peter Maydell 2022-04-08 15:15:30 +01:00
parent 3c64a42c0b
commit c6dd2f9950
4 changed files with 45 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
hw/intc/arm_gicv3_its.c
View File

@ -1163,6 +1163,29 @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt)
return update_ite(s, eventid, &dte, &ite) ? CMD_CONTINUE_OK : CMD_STALL;
}
static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt)
{
VTEntry vte;
uint32_t vpeid;
ItsCmdResult cmdres;
if (!its_feature_virtual(s)) {
return CMD_CONTINUE;
}
vpeid = FIELD_EX64(cmdpkt[1], VINVALL_1, VPEID);
trace_gicv3_its_cmd_vinvall(vpeid);
cmdres = lookup_vte(s, __func__, vpeid, &vte);
if (cmdres != CMD_CONTINUE_OK) {
return cmdres;
}
gicv3_redist_vinvall(&s->gicv3->cpu[vte.rdbase], vte.vptaddr << 16);
return CMD_CONTINUE_OK;
}
static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt)
{
uint32_t devid, eventid;
@ -1364,6 +1387,9 @@ static void process_cmdq(GICv3ITSState *s)
case GITS_CMD_VMOVI:
result = process_vmovi(s, cmdpkt);
break;
case GITS_CMD_VINVALL:
result = process_vinvall(s, cmdpkt);
break;
default:
trace_gicv3_its_cmd_unknown(cmd);
break;

5
hw/intc/arm_gicv3_redist.c
View File

@ -818,6 +818,11 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr,
*/
}
void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr)
{
/* The redistributor handling will be added in a subsequent commit */
}
void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr)
{
/*

13
hw/intc/gicv3_internal.h
View File

@ -335,6 +335,7 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define GITS_CMD_VMAPP 0x29
#define GITS_CMD_VMAPTI 0x2A
#define GITS_CMD_VMAPI 0x2B
#define GITS_CMD_VINVALL 0x2D
/* MAPC command fields */
#define ICID_LENGTH 16
@ -411,6 +412,9 @@ FIELD(VMOVI_1, VPEID, 32, 16)
FIELD(VMOVI_2, D, 0, 1)
FIELD(VMOVI_2, DOORBELL, 32, 32)
/* VINVALL command fields */
FIELD(VINVALL_1, VPEID, 32, 16)
/*
* 12 bytes Interrupt translation Table Entry size
* as per Table 5.3 in GICv3 spec
@ -637,6 +641,15 @@ void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest);
void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr,
GICv3CPUState *dest, uint64_t dest_vptaddr,
int irq, int doorbell);
/**
* gicv3_redist_vinvall:
* @cs: GICv3CPUState
* @vptaddr: address of VLPI pending table
*
* On redistributor @cs, invalidate all cached information associated
* with the vCPU defined by @vptaddr.
*/
void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr);
void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
void gicv3_init_cpuif(GICv3State *s);

1
hw/intc/trace-events
View File

@ -194,6 +194,7 @@ gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr
gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64
gicv3_its_cmd_vsync(void) "GICv3 ITS: command VSYNC"
gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell) "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x"
gicv3_its_cmd_vinvall(uint32_t vpeid) "GICv3 ITS: command VINVALL vPEID 0x%x"
gicv3_its_cmd_unknown(unsigned cmd) "GICv3 ITS: unknown command 0x%x"
gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x"
gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x"