mirror of https://github.com/proxmox/mirror_qemu
hw/nvram: NPCM7xx OTP device model
This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Havard Skinnemoen
Peter Maydell
parent
4e89ccd685
commit
c752bb079b
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@ -34,6 +34,10 @@
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#define NPCM7XX_MMIO_BA (0x80000000)
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#define NPCM7XX_MMIO_SZ (0x7ffd0000)
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/* OTP key storage and fuse strap array */
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#define NPCM7XX_OTP1_BA (0xf0189000)
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#define NPCM7XX_OTP2_BA (0xf018a000)
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/* Core system modules. */
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#define NPCM7XX_L2C_BA (0xf03fc000)
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#define NPCM7XX_CPUP_BA (0xf03fe000)
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@ -144,6 +148,20 @@ void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
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arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
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}
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static void npcm7xx_init_fuses(NPCM7xxState *s)
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{
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NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
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uint32_t value;
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/*
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* The initial mask of disabled modules indicates the chip derivative (e.g.
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* NPCM750 or NPCM730).
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*/
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value = tswap32(nc->disabled_modules);
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npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
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sizeof(value));
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}
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static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
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{
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return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
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@ -164,6 +182,10 @@ static void npcm7xx_init(Object *obj)
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object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
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"power-on-straps");
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object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
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object_initialize_child(obj, "otp1", &s->key_storage,
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TYPE_NPCM7XX_KEY_STORAGE);
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object_initialize_child(obj, "otp2", &s->fuse_array,
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TYPE_NPCM7XX_FUSE_ARRAY);
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for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
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object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
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@ -232,6 +254,13 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
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/* OTP key storage and fuse strap array. Cannot fail. */
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sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
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sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
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npcm7xx_init_fuses(s);
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/* Timer Modules (TIM). Cannot fail. */
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
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for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
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@ -4,6 +4,7 @@ softmmu_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c'))
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softmmu_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c'))
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softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
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softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
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softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
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softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
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@ -0,0 +1,440 @@
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/*
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* Nuvoton NPCM7xx OTP (Fuse Array) Interface
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/nvram/npcm7xx_otp.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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/* Each module has 4 KiB of register space. Only a fraction of it is used. */
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#define NPCM7XX_OTP_REGS_SIZE (4 * KiB)
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/* 32-bit register indices. */
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typedef enum NPCM7xxOTPRegister {
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NPCM7XX_OTP_FST,
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NPCM7XX_OTP_FADDR,
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NPCM7XX_OTP_FDATA,
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NPCM7XX_OTP_FCFG,
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/* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */
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NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t),
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NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t),
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NPCM7XX_OTP_FCTL,
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NPCM7XX_OTP_REGS_END,
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} NPCM7xxOTPRegister;
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/* Register field definitions. */
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#define FST_RIEN BIT(2)
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#define FST_RDST BIT(1)
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#define FST_RDY BIT(0)
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#define FST_RO_MASK (FST_RDST | FST_RDY)
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#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10)
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#define FADDR_BITPOS(rv) extract32((rv), 10, 3)
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#define FDATA_CLEAR 0x00000001
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#define FCFG_FDIS BIT(31)
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#define FCFG_FCFGLK_MASK 0x00ff0000
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#define FCTL_PROG_CMD1 0x00000001
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#define FCTL_PROG_CMD2 0xbf79e5d0
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#define FCTL_READ_CMD 0x00000002
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/**
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* struct NPCM7xxOTPClass - OTP module class.
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* @parent: System bus device class.
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* @mmio_ops: MMIO register operations for this type of module.
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*
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* The two OTP modules (key-storage and fuse-array) have slightly different
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* behavior, so we give them different MMIO register operations.
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*/
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struct NPCM7xxOTPClass {
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SysBusDeviceClass parent;
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const MemoryRegionOps *mmio_ops;
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};
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#define NPCM7XX_OTP_CLASS(klass) \
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OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP)
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#define NPCM7XX_OTP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP)
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static uint8_t ecc_encode_nibble(uint8_t n)
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{
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uint8_t result = n;
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result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4;
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result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5;
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result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6;
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result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7;
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return result;
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}
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void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
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unsigned int offset, unsigned int len)
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{
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const uint8_t *src = data;
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uint8_t *dst = &s->array[offset];
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while (len-- > 0) {
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uint8_t c = *src++;
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*dst++ = ecc_encode_nibble(extract8(c, 0, 4));
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*dst++ = ecc_encode_nibble(extract8(c, 4, 4));
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}
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}
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/* Common register read handler for both OTP classes. */
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static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg)
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{
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uint32_t value = 0;
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switch (reg) {
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case NPCM7XX_OTP_FST:
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case NPCM7XX_OTP_FADDR:
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case NPCM7XX_OTP_FDATA:
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case NPCM7XX_OTP_FCFG:
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value = s->regs[reg];
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break;
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case NPCM7XX_OTP_FCTL:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: read from write-only FCTL register\n",
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DEVICE(s)->canonical_path);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n",
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DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
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break;
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}
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return value;
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}
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/* Read a byte from the OTP array into the data register. */
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static void npcm7xx_otp_read_array(NPCM7xxOTPState *s)
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{
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uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
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s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)];
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s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
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}
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/* Program a byte from the data register into the OTP array. */
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static void npcm7xx_otp_program_array(NPCM7xxOTPState *s)
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{
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uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
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/* Bits can only go 0->1, never 1->0. */
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s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr));
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s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
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}
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/* Compute the next value of the FCFG register. */
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static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value)
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{
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uint32_t lock_mask;
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uint32_t value;
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/*
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* FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15)
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* and FRDLK (0..7) that are read-only.
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*/
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lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8;
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lock_mask |= lock_mask >> 8;
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/* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */
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value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK);
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/* Preserve read-only bits in FPRGLK and FRDLK */
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value |= cur_value & lock_mask;
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/* Set all bits that aren't read-only. */
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value |= new_value & ~lock_mask;
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return value;
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}
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/* Common register write handler for both OTP classes. */
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static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg,
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uint32_t value)
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{
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switch (reg) {
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case NPCM7XX_OTP_FST:
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/* RDST is cleared by writing 1 to it. */
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if (value & FST_RDST) {
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s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST;
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}
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/* Preserve read-only and write-one-to-clear bits */
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value &= ~FST_RO_MASK;
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value |= s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK;
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break;
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case NPCM7XX_OTP_FADDR:
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break;
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case NPCM7XX_OTP_FDATA:
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/*
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* This register is cleared by writing a magic value to it; no other
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* values can be written.
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*/
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if (value == FDATA_CLEAR) {
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value = 0;
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} else {
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value = s->regs[NPCM7XX_OTP_FDATA];
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}
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break;
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case NPCM7XX_OTP_FCFG:
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value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value);
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break;
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case NPCM7XX_OTP_FCTL:
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switch (value) {
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case FCTL_READ_CMD:
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npcm7xx_otp_read_array(s);
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break;
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case FCTL_PROG_CMD1:
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/*
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* Programming requires writing two separate magic values to this
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* register; this is the first one. Just store it so it can be
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* verified later when the second magic value is received.
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*/
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break;
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case FCTL_PROG_CMD2:
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/*
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* Only initiate programming if we received the first half of the
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* command immediately before this one.
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*/
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if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) {
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npcm7xx_otp_program_array(s);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: unrecognized FCNTL value 0x%" PRIx32 "\n",
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DEVICE(s)->canonical_path, value);
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break;
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}
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if (value != FCTL_PROG_CMD1) {
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value = 0;
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n",
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DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
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return;
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}
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s->regs[reg] = value;
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}
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/* Register read handler specific to the fuse array OTP module. */
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static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
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NPCM7xxOTPState *s = opaque;
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uint32_t value;
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/*
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* Only the Fuse Strap register needs special handling; all other registers
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* work the same way for both kinds of OTP modules.
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*/
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if (reg != NPCM7XX_OTP_FUSTRAP) {
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value = npcm7xx_otp_read(s, reg);
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} else {
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/* FUSTRAP is stored as three copies in the OTP array. */
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uint32_t fustrap[3];
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memcpy(fustrap, &s->array[0], sizeof(fustrap));
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/* Determine value by a majority vote on each bit. */
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value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) |
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(fustrap[1] & fustrap[2]);
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}
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return value;
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}
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/* Register write handler specific to the fuse array OTP module. */
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static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
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NPCM7xxOTPState *s = opaque;
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/*
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* The Fuse Strap register is read-only. Other registers are handled by
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* common code.
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*/
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if (reg != NPCM7XX_OTP_FUSTRAP) {
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npcm7xx_otp_write(s, reg, v);
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}
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}
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static const MemoryRegionOps npcm7xx_fuse_array_ops = {
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.read = npcm7xx_fuse_array_read,
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.write = npcm7xx_fuse_array_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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/* Register read handler specific to the key storage OTP module. */
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static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
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NPCM7xxOTPState *s = opaque;
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/*
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* Only the Fuse Key Index register needs special handling; all other
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* registers work the same way for both kinds of OTP modules.
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*/
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if (reg != NPCM7XX_OTP_FKEYIND) {
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return npcm7xx_otp_read(s, reg);
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}
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qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
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return s->regs[NPCM7XX_OTP_FKEYIND];
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}
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/* Register write handler specific to the key storage OTP module. */
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static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
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NPCM7xxOTPState *s = opaque;
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/*
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* Only the Fuse Key Index register needs special handling; all other
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* registers work the same way for both kinds of OTP modules.
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*/
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if (reg != NPCM7XX_OTP_FKEYIND) {
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npcm7xx_otp_write(s, reg, v);
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return;
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}
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qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
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|
||||
s->regs[NPCM7XX_OTP_FKEYIND] = v;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps npcm7xx_key_storage_ops = {
|
||||
.read = npcm7xx_key_storage_read,
|
||||
.write = npcm7xx_key_storage_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
.unaligned = false,
|
||||
},
|
||||
};
|
||||
|
||||
static void npcm7xx_otp_enter_reset(Object *obj, ResetType type)
|
||||
{
|
||||
NPCM7xxOTPState *s = NPCM7XX_OTP(obj);
|
||||
|
||||
memset(s->regs, 0, sizeof(s->regs));
|
||||
|
||||
s->regs[NPCM7XX_OTP_FST] = 0x00000001;
|
||||
s->regs[NPCM7XX_OTP_FCFG] = 0x20000000;
|
||||
}
|
||||
|
||||
static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
|
||||
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
|
||||
SysBusDevice *sbd = &s->parent;
|
||||
|
||||
memset(s->array, 0, sizeof(s->array));
|
||||
|
||||
memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
|
||||
NPCM7XX_OTP_REGS_SIZE);
|
||||
sysbus_init_mmio(sbd, &s->mmio);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_npcm7xx_otp = {
|
||||
.name = "npcm7xx-otp",
|
||||
.version_id = 0,
|
||||
.minimum_version_id = 0,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, NPCM7xxOTPState, NPCM7XX_OTP_NR_REGS),
|
||||
VMSTATE_UINT8_ARRAY(array, NPCM7xxOTPState, NPCM7XX_OTP_ARRAY_BYTES),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
QEMU_BUILD_BUG_ON(NPCM7XX_OTP_REGS_END > NPCM7XX_OTP_NR_REGS);
|
||||
|
||||
dc->realize = npcm7xx_otp_realize;
|
||||
dc->vmsd = &vmstate_npcm7xx_otp;
|
||||
rc->phases.enter = npcm7xx_otp_enter_reset;
|
||||
}
|
||||
|
||||
static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
|
||||
|
||||
oc->mmio_ops = &npcm7xx_key_storage_ops;
|
||||
}
|
||||
|
||||
static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
|
||||
|
||||
oc->mmio_ops = &npcm7xx_fuse_array_ops;
|
||||
}
|
||||
|
||||
static const TypeInfo npcm7xx_otp_types[] = {
|
||||
{
|
||||
.name = TYPE_NPCM7XX_OTP,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(NPCM7xxOTPState),
|
||||
.class_size = sizeof(NPCM7xxOTPClass),
|
||||
.class_init = npcm7xx_otp_class_init,
|
||||
.abstract = true,
|
||||
},
|
||||
{
|
||||
.name = TYPE_NPCM7XX_KEY_STORAGE,
|
||||
.parent = TYPE_NPCM7XX_OTP,
|
||||
.class_init = npcm7xx_key_storage_class_init,
|
||||
},
|
||||
{
|
||||
.name = TYPE_NPCM7XX_FUSE_ARRAY,
|
||||
.parent = TYPE_NPCM7XX_OTP,
|
||||
.class_init = npcm7xx_fuse_array_class_init,
|
||||
},
|
||||
};
|
||||
DEFINE_TYPES(npcm7xx_otp_types);
|
||||
|
|
@ -20,6 +20,7 @@
|
|||
#include "hw/cpu/a9mpcore.h"
|
||||
#include "hw/misc/npcm7xx_clk.h"
|
||||
#include "hw/misc/npcm7xx_gcr.h"
|
||||
#include "hw/nvram/npcm7xx_otp.h"
|
||||
#include "hw/timer/npcm7xx_timer.h"
|
||||
#include "target/arm/cpu.h"
|
||||
|
||||
|
|
@ -68,6 +69,8 @@ typedef struct NPCM7xxState {
|
|||
NPCM7xxGCRState gcr;
|
||||
NPCM7xxCLKState clk;
|
||||
NPCM7xxTimerCtrlState tim[3];
|
||||
NPCM7xxOTPState key_storage;
|
||||
NPCM7xxOTPState fuse_array;
|
||||
} NPCM7xxState;
|
||||
|
||||
#define TYPE_NPCM7XX "npcm7xx"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Nuvoton NPCM7xx OTP (Fuse Array) Interface
|
||||
*
|
||||
* Copyright 2020 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef NPCM7XX_OTP_H
|
||||
#define NPCM7XX_OTP_H
|
||||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/sysbus.h"
|
||||
|
||||
/* Each OTP module holds 8192 bits of one-time programmable storage */
|
||||
#define NPCM7XX_OTP_ARRAY_BITS (8192)
|
||||
#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / BITS_PER_BYTE)
|
||||
|
||||
/* Fuse array offsets */
|
||||
#define NPCM7XX_FUSE_FUSTRAP (0)
|
||||
#define NPCM7XX_FUSE_CP_FUSTRAP (12)
|
||||
#define NPCM7XX_FUSE_DAC_CALIB (16)
|
||||
#define NPCM7XX_FUSE_ADC_CALIB (24)
|
||||
#define NPCM7XX_FUSE_DERIVATIVE (64)
|
||||
#define NPCM7XX_FUSE_TEST_SIG (72)
|
||||
#define NPCM7XX_FUSE_DIE_LOCATION (74)
|
||||
#define NPCM7XX_FUSE_GP1 (80)
|
||||
#define NPCM7XX_FUSE_GP2 (128)
|
||||
|
||||
/*
|
||||
* Number of registers in our device state structure. Don't change this without
|
||||
* incrementing the version_id in the vmstate.
|
||||
*/
|
||||
#define NPCM7XX_OTP_NR_REGS (0x18 / sizeof(uint32_t))
|
||||
|
||||
/**
|
||||
* struct NPCM7xxOTPState - Device state for one OTP module.
|
||||
* @parent: System bus device.
|
||||
* @mmio: Memory region through which registers are accessed.
|
||||
* @regs: Register contents.
|
||||
* @array: OTP storage array.
|
||||
*/
|
||||
typedef struct NPCM7xxOTPState {
|
||||
SysBusDevice parent;
|
||||
|
||||
MemoryRegion mmio;
|
||||
uint32_t regs[NPCM7XX_OTP_NR_REGS];
|
||||
uint8_t array[NPCM7XX_OTP_ARRAY_BYTES];
|
||||
} NPCM7xxOTPState;
|
||||
|
||||
#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
|
||||
#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
|
||||
|
||||
#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
|
||||
#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
|
||||
|
||||
typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
|
||||
|
||||
/**
|
||||
* npcm7xx_otp_array_write - ECC encode and write data to OTP array.
|
||||
* @s: OTP module.
|
||||
* @data: Data to be encoded and written.
|
||||
* @offset: Offset of first byte to be written in the OTP array.
|
||||
* @len: Number of bytes before ECC encoding.
|
||||
*
|
||||
* Each nibble of data is encoded into a byte, so the number of bytes written
|
||||
* to the array will be @len * 2.
|
||||
*/
|
||||
extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
|
||||
unsigned int offset, unsigned int len);
|
||||
|
||||
#endif /* NPCM7XX_OTP_H */
|
||||
Loading…
Reference in New Issue