From c80f84e3c037ebaebcec48f59c65be02a6d76a89 Mon Sep 17 00:00:00 2001 From: j_mayer Date: Sun, 30 Sep 2007 01:18:26 +0000 Subject: [PATCH] Implement Process Priority Register as defined in the PowerPC 2.04 spec. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3282 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-ppc/op.c | 8 ++++++++ target-ppc/op_helper.c | 8 ++++++++ target-ppc/op_helper.h | 3 +++ target-ppc/translate.c | 20 ++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target-ppc/op.c b/target-ppc/op.c index 46843d790f..fa8477ab9f 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -295,6 +295,14 @@ void OPPROTO op_store_xer (void) RETURN(); } +#if defined(TARGET_PPC64) +void OPPROTO op_store_pri (void) +{ + do_store_pri(PARAM1); + RETURN(); +} +#endif + #if !defined(CONFIG_USER_ONLY) /* Segment registers load and store */ void OPPROTO op_load_sr (void) diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 08441caaec..d75331722d 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -112,6 +112,14 @@ void do_store_xer (void) xer_bc = (T0 >> XER_BC) & 0x7F; } +#if defined(TARGET_PPC64) +void do_store_pri (int prio) +{ + env->spr[SPR_PPR] &= ~0x001C000000000000ULL; + env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50; +} +#endif + void do_load_fpscr (void) { /* The 32 MSB of the target fpr are undefined. diff --git a/target-ppc/op_helper.h b/target-ppc/op_helper.h index 6c0d2fbf92..c5b4f2d19b 100644 --- a/target-ppc/op_helper.h +++ b/target-ppc/op_helper.h @@ -57,6 +57,9 @@ void do_load_cr (void); void do_store_cr (uint32_t mask); void do_load_xer (void); void do_store_xer (void); +#if defined(TARGET_PPC64) +void do_store_pri (int prio); +#endif void do_load_fpscr (void); void do_store_fpscr (uint32_t mask); target_ulong ppc_load_dump_spr (int sprn); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f4ff22e385..08cd92cde7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1124,6 +1124,26 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) } else if (unlikely(Rc(ctx->opcode) != 0)) { gen_op_load_gpr_T0(rs); gen_set_Rc0(ctx); +#if defined(TARGET_PPC64) + } else { + switch (rs) { + case 1: + /* Set process priority to low */ + gen_op_store_pri(2); + break; + case 6: + /* Set process priority to medium-low */ + gen_op_store_pri(3); + break; + case 2: + /* Set process priority to normal */ + gen_op_store_pri(4); + break; + default: + /* nop */ + break; + } +#endif } }