mirror of https://github.com/proxmox/mirror_qemu
Code provision for PowerPC 64 MMU model support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3186 c046a42c-6fe2-441c-8c8c-71466251a162master
j_mayer
parent
8b67546f65
commit
caa4039ced
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@ -77,24 +77,62 @@ static inline void pte_invalidate (target_ulong *pte0)
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*pte0 &= ~0x80000000;
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}
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#if defined(TARGET_PPC64)
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static inline int pte64_is_valid (target_ulong pte0)
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{
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return pte0 & 0x0000000000000001ULL ? 1 : 0;
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}
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static inline void pte64_invalidate (target_ulong *pte0)
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{
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*pte0 &= ~0x0000000000000001ULL;
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}
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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#if defined(TARGET_PPC64)
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#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
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#endif
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static int pte_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1, int h, int rw)
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static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
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target_ulong pte0, target_ulong pte1,
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int h, int rw)
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{
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int access, ret;
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev;
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access = 0;
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ret = -1;
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/* Check validity and table match */
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if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptev = pte64_is_valid(pte0);
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pteh = (pte0 >> 1) & 1;
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} else
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#endif
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{
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ptev = pte_is_valid(pte0);
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pteh = (pte0 >> 6) & 1;
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}
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if (ptev && h == pteh) {
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/* Check vsid & api */
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if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptem = pte0 & PTE64_PTEM_MASK;
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mmask = PTE64_CHECK_MASK;
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} else
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#endif
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{
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ptem = pte0 & PTE_PTEM_MASK;
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mmask = PTE_CHECK_MASK;
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}
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (target_ulong)-1) {
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
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if (loglevel > 0)
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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if (loglevel != 0)
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fprintf(logfile, "Bad RPN/WIMG/PP\n");
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return -3;
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}
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@ -143,6 +181,20 @@ static int pte_check (mmu_ctx_t *ctx,
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return ret;
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}
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static int pte32_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1, int h, int rw)
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{
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return _pte_check(ctx, 0, pte0, pte1, h, rw);
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}
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#if defined(TARGET_PPC64)
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static int pte64_check (mmu_ctx_t *ctx,
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target_ulong pte0, target_ulong pte1, int h, int rw)
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{
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return _pte_check(ctx, 1, pte0, pte1, h, rw);
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}
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#endif
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static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
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int ret, int rw)
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{
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@ -305,7 +357,7 @@ static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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}
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#endif
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switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
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switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
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case -3:
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/* TLB inconsistency */
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return -1;
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@ -440,26 +492,36 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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}
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/* PTE table lookup */
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static int find_pte (mmu_ctx_t *ctx, int h, int rw)
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static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
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{
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target_ulong base, pte0, pte1;
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int i, good = -1;
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int ret;
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int ret, r;
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ret = -1; /* No entry found */
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base = ctx->pg_addr[h];
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for (i = 0; i < 8; i++) {
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4);
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#if defined(TARGET_PPC64)
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if (is_64b) {
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pte0 = ldq_phys(base + (i * 16));
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pte1 = ldq_phys(base + (i * 16) + 8);
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r = pte64_check(ctx, pte0, pte1, h, rw);
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} else
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#endif
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{
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pte0 = ldl_phys(base + (i * 8));
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pte1 = ldl_phys(base + (i * 8) + 4);
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r = pte32_check(ctx, pte0, pte1, h, rw);
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}
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
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" 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
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base + (i * 8), pte0, pte1,
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pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
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(int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
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}
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#endif
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switch (pte_check(ctx, pte0, pte1, h, rw)) {
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switch (r) {
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case -3:
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/* PTE inconsistency */
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return -1;
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@ -494,59 +556,183 @@ static int find_pte (mmu_ctx_t *ctx, int h, int rw)
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#endif
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/* Update page flags */
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pte1 = ctx->raddr;
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if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
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stl_phys_notdirty(base + (good * 8) + 4, pte1);
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if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
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#if defined(TARGET_PPC64)
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if (is_64b) {
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stq_phys_notdirty(base + (good * 16) + 8, pte1);
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} else
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#endif
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{
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stl_phys_notdirty(base + (good * 8) + 4, pte1);
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}
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}
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}
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return ret;
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}
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static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
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{
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return _find_pte(ctx, 0, h, rw);
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}
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#if defined(TARGET_PPC64)
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static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
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{
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return _find_pte(ctx, 1, h, rw);
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}
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#endif
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static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
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{
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#if defined(TARGET_PPC64)
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if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
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PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE)
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return find_pte64(ctx, h, rw);
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#endif
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return find_pte32(ctx, h, rw);
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}
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static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
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int sdr_sh,
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target_phys_addr_t hash,
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target_phys_addr_t mask)
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{
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return (sdr1 & 0xFFFF0000) | (hash & mask);
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return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
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}
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#if defined(TARGET_PPC64)
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static int slb_lookup (CPUState *env, target_ulong eaddr,
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target_ulong *vsid, target_ulong *page_mask, int *attr)
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{
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target_phys_addr_t sr_base;
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target_ulong mask;
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uint64_t tmp64;
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uint32_t tmp;
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int n, ret;
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int slb_nr;
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ret = -5;
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sr_base = env->spr[SPR_ASR];
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mask = 0x0000000000000000ULL; /* Avoid gcc warning */
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#if 0 /* XXX: Fix this */
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slb_nr = env->slb_nr;
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#else
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slb_nr = 32;
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#endif
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for (n = 0; n < slb_nr; n++) {
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tmp64 = ldq_phys(sr_base);
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if (tmp64 & 0x0000000008000000ULL) {
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/* SLB entry is valid */
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switch (tmp64 & 0x0000000006000000ULL) {
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case 0x0000000000000000ULL:
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/* 256 MB segment */
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mask = 0xFFFFFFFFF0000000ULL;
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break;
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case 0x0000000002000000ULL:
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/* 1 TB segment */
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mask = 0xFFFF000000000000ULL;
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break;
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case 0x0000000004000000ULL:
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case 0x0000000006000000ULL:
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/* Reserved => segment is invalid */
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continue;
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}
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if ((eaddr & mask) == (tmp64 & mask)) {
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/* SLB match */
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tmp = ldl_phys(sr_base + 8);
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*vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
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*page_mask = ~mask;
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*attr = tmp & 0xFF;
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ret = 0;
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break;
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}
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}
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sr_base += 12;
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}
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return ret;
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}
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#endif /* defined(TARGET_PPC64) */
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/* Perform segment based translation */
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static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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target_phys_addr_t sdr, hash, mask;
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target_ulong sr, vsid, pgidx;
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int ret = -1, ret2;
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sr = env->sr[eaddr >> 28];
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
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ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, eaddr >> 28, sr, env->nip,
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env->lr, msr_ir, msr_dr, msr_pr, rw, type);
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}
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target_phys_addr_t sdr, hash, mask, sdr_mask;
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target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
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#if defined(TARGET_PPC64)
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int attr;
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#endif
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ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
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if ((sr & 0x80000000) == 0) {
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int ds, nx, vsid_sh, sdr_sh;
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int ret, ret2;
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#if defined(TARGET_PPC64)
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if (PPC_MMU(env) == PPC_FLAGS_MMU_64B) {
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ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
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if (ret < 0)
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return ret;
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ctx->key = ((attr & 0x40) && msr_pr == 1) ||
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((attr & 0x80) && msr_pr == 0) ? 1 : 0;
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ds = 0;
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nx = attr & 0x20 ? 1 : 0;
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vsid_mask = 0x00003FFFFFFFFF80ULL;
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vsid_sh = 7;
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sdr_sh = 18;
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sdr_mask = 0x3FF80;
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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sr = env->sr[eaddr >> 28];
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page_mask = 0x0FFFFFFF;
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ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
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((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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vsid_mask = 0x01FFFFC0;
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vsid_sh = 6;
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sdr_sh = 16;
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sdr_mask = 0xFFC0;
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0) {
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fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
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" nip=0x" ADDRX " lr=0x" ADDRX
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip,
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env->lr, msr_ir, msr_dr, msr_pr, rw, type);
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}
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if (!ds && loglevel != 0) {
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fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
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ctx->key, sr & 0x10000000);
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}
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#endif
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}
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ret = -1;
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if (!ds) {
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
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if (type != ACCESS_CODE || nx == 0) {
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/* Page address translation */
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pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
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vsid = sr & 0x00FFFFFF;
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hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
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pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
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hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
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/* Primary table address */
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sdr = env->sdr1;
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mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
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ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
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mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
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ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
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/* Secondary table address */
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hash = (~hash) & 0x01FFFFC0;
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ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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hash = (~hash) & vsid_mask;
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ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
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#if defined(TARGET_PPC64)
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if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
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PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE) {
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/* Only 5 bits of the page index are used in the AVPN */
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ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
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} else
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#endif
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{
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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}
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/* Initialize real address with an invalid value */
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ctx->raddr = (target_ulong)-1;
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if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
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@ -562,7 +748,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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}
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#endif
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/* Primary table lookup */
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ret = find_pte(ctx, 0, rw);
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ret = find_pte(env, ctx, 0, rw);
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if (ret < 0) {
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/* Secondary table lookup */
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#if defined (DEBUG_MMU)
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@ -574,7 +760,7 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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(uint32_t)hash, ctx->pg_addr[1]);
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}
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#endif
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ret2 = find_pte(ctx, 1, rw);
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ret2 = find_pte(env, ctx, 1, rw);
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if (ret2 != -1)
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ret = ret2;
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}
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@ -835,29 +1021,54 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx,
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ctx->raddr = eaddr;
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ctx->prot = PAGE_READ;
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ret = 0;
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if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
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/* 403 family add some particular protections,
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* using PBL/PBU registers for accesses with no translation.
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*/
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in_plb =
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/* Check PLB validity */
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(env->pb[0] < env->pb[1] &&
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/* and address in plb area */
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eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
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(env->pb[2] < env->pb[3] &&
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eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
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if (in_plb ^ msr_px) {
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/* Access in protected area */
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if (rw == 1) {
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/* Access is not allowed */
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ret = -2;
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}
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} else {
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/* Read-write access is allowed */
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ctx->prot |= PAGE_WRITE;
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}
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} else {
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switch (PPC_MMU(env)) {
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case PPC_FLAGS_MMU_32B:
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case PPC_FLAGS_MMU_SOFT_6xx:
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case PPC_FLAGS_MMU_601:
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case PPC_FLAGS_MMU_SOFT_4xx:
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ctx->prot |= PAGE_WRITE;
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break;
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_MMU_64B:
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case PPC_FLAGS_MMU_64BRIDGE:
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#endif
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/* Real address are 60 bits long */
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ctx->raddr &= 0x0FFFFFFFFFFFFFFFUL;
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ctx->prot |= PAGE_WRITE;
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break;
|
||||
case PPC_FLAGS_MMU_403:
|
||||
if (unlikely(msr_pe != 0)) {
|
||||
/* 403 family add some particular protections,
|
||||
* using PBL/PBU registers for accesses with no translation.
|
||||
*/
|
||||
in_plb =
|
||||
/* Check PLB validity */
|
||||
(env->pb[0] < env->pb[1] &&
|
||||
/* and address in plb area */
|
||||
eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
|
||||
(env->pb[2] < env->pb[3] &&
|
||||
eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
|
||||
if (in_plb ^ msr_px) {
|
||||
/* Access in protected area */
|
||||
if (rw == 1) {
|
||||
/* Access is not allowed */
|
||||
ret = -2;
|
||||
}
|
||||
} else {
|
||||
/* Read-write access is allowed */
|
||||
ctx->prot |= PAGE_WRITE;
|
||||
}
|
||||
}
|
||||
case PPC_FLAGS_MMU_BOOKE:
|
||||
ctx->prot |= PAGE_WRITE;
|
||||
break;
|
||||
case PPC_FLAGS_MMU_BOOKE_FSL:
|
||||
/* XXX: TODO */
|
||||
cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
||||
break;
|
||||
default:
|
||||
cpu_abort(env, "Unknown or invalid MMU model\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
Loading…
Reference in New Issue