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target/xtensa: don't generate extra EXCP_DEBUG on exception 

target/xtensa used to generate an extra EXCP_DEBUG exception before the
first instruction executed after an interrupt or an exception is taken
to allow single-stepping that instruction in the debugger.
This is no longer needed after the following commits:
a7ba744f40 ("tcg/cpu-exec: precise single-stepping after an exception")
ba3c35d9c4 ("tcg/cpu-exec: precise single-stepping after an interrupt")
Drop exception state tracking/extra EXCP_DEBUG generation code.

Cc: qemu-stable@nongnu.org # v5.1, v5.2, v6.0
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
master
Max Filippov 2021-04-15 13:38:08 -07:00
parent 972e848b53
commit cb2d627a00
4 changed files with 0 additions and 19 deletions
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1
target/xtensa/cpu.c
View File

@ -79,7 +79,6 @@ static void xtensa_cpu_reset(DeviceState *dev)
xcc->parent_reset(dev);
env->exception_taken = 0;
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
env->sregs[LITBASE] &= ~1;
#ifndef CONFIG_USER_ONLY

7
target/xtensa/cpu.h
View File

@ -540,7 +540,6 @@ typedef struct CPUXtensaState {
uint32_t ccount_base;
#endif
int exception_taken;
int yield_needed;
unsigned static_vectors;
@ -711,7 +710,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_TBFLAG_ICOUNT 0x20
#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000
#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
#define XTENSA_TBFLAG_WINDOW_SHIFT 15
#define XTENSA_TBFLAG_YIELD 0x20000
@ -732,8 +730,6 @@ typedef XtensaCPU ArchCPU;
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
CPUState *cs = env_cpu(env);
*pc = env->pc;
*cs_base = 0;
*flags = 0;
@ -782,9 +778,6 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
}
if (cs->singlestep_enabled && env->exception_taken) {
*flags |= XTENSA_TBFLAG_EXCEPTION;
}
if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
(env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
uint32_t windowstart = xtensa_replicate_windowstart(env) >>

5
target/xtensa/exc_helper.c
View File

@ -40,9 +40,6 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
if (excp == EXCP_YIELD) {
env->yield_needed = 0;
}
if (excp == EXCP_DEBUG) {
env->exception_taken = 0;
}
cpu_loop_exit(cs);
}
@ -197,7 +194,6 @@ static void handle_interrupt(CPUXtensaState *env)
}
env->sregs[PS] |= PS_EXCM;
}
env->exception_taken = 1;
}
}
@ -242,7 +238,6 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
vector = env->config->exception_vector[cs->exception_index];
env->pc = relocated_vector(env, vector);
env->exception_taken = 1;
} else {
qemu_log_mask(CPU_LOG_INT,
"%s(pc = %08x) bad exception_index: %d\n",

6
target/xtensa/translate.c
View File

@ -1279,12 +1279,6 @@ static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
dc->base.is_jmp = DISAS_NORETURN;
return;
}
if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) {
gen_exception(dc, EXCP_DEBUG);
dc->base.pc_next = dc->pc + 1;
dc->base.is_jmp = DISAS_NORETURN;
return;
}
if (dc->icount) {
TCGLabel *label = gen_new_label();