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Block-TLB support and linux-user fixes for hppa target 

All 32-bit hppa CPUs allow a fixed number of TLB entries to have a
 different page size than the default 4k.
 Those are called "Block-TLBs" and are created at startup by the
 operating system and managed by the firmware of hppa machines
 through the firmware PDC_BLOCK_TLB call.
 
 This patchset adds the necessary glue to SeaBIOS-hppa and
 qemu to allow up to 16 BTLB entries in the emulation.
 
 Two patches from Mikulas Patocka fix signal delivery issues
 in linux-user on hppa.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZQnz0wAKCRD3ErUQojoP
 X6NDAP9F1Huhceot8peohGodRDOhnXWfDcjQZSDvadieKv/rJQEA60Z5QV5VlQgw
 SyUT4AcoiB7N4nvS+iDa+6dKfRH/YQM=
 =kqqt
 -----END PGP SIGNATURE-----

Merge tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa into staging

Block-TLB support and linux-user fixes for hppa target

All 32-bit hppa CPUs allow a fixed number of TLB entries to have a
different page size than the default 4k.
Those are called "Block-TLBs" and are created at startup by the
operating system and managed by the firmware of hppa machines
through the firmware PDC_BLOCK_TLB call.

This patchset adds the necessary glue to SeaBIOS-hppa and
qemu to allow up to 16 BTLB entries in the emulation.

Two patches from Mikulas Patocka fix signal delivery issues
in linux-user on hppa.

# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZQnz0wAKCRD3ErUQojoP
# X6NDAP9F1Huhceot8peohGodRDOhnXWfDcjQZSDvadieKv/rJQEA60Z5QV5VlQgw
# SyUT4AcoiB7N4nvS+iDa+6dKfRH/YQM=
# =kqqt
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 19 Sep 2023 15:17:39 EDT
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa:
  linux-user/hppa: lock both words of function descriptor
  linux-user/hppa: clear the PSW 'N' bit when delivering signals
  target/hppa: Wire up diag instruction to support BTLB
  target/hppa: Extract diagnose immediate value
  target/hppa: Add BTLB support to hppa TLB functions
  target/hppa: Report and clear BTLBs via fw_cfg at startup
  target/hppa: Allow up to 16 BTLB entries
  target/hppa: Update to SeaBIOS-hppa version 9

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
master
Stefan Hajnoczi 2023-09-20 13:56:01 -04:00
parent 4907644841 5b1270ef14
commit cb8a8b2ca9
11 changed files with 188 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
hw/hppa/machine.c
View File

@ -133,14 +133,10 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
g_memdup(&val, sizeof(val)), sizeof(val));
val = cpu_to_le64(HPPA_TLB_ENTRIES);
val = cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES);
fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
g_memdup(&val, sizeof(val)), sizeof(val));
val = cpu_to_le64(HPPA_BTLB_ENTRIES);
fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries",
g_memdup(&val, sizeof(val)), sizeof(val));
val = cpu_to_le64(HPA_POWER_BUTTON);
fw_cfg_add_file(fw_cfg, "/etc/power-button-addr",
g_memdup(&val, sizeof(val)), sizeof(val));
@ -433,6 +429,10 @@ static void hppa_machine_reset(MachineState *ms, ShutdownCause reason)
cs->exception_index = -1;
cs->halted = 0;
/* clear any existing TLB and BTLB entries */
memset(cpu[i]->env.tlb, 0, sizeof(cpu[i]->env.tlb));
cpu[i]->env.tlb_last = HPPA_BTLB_ENTRIES;
}
/* already initialized by machine_hppa_init()? */

6
linux-user/hppa/signal.c
View File

@ -149,16 +149,18 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
target_ulong *fdesc, dest;
haddr &= -4;
if (!lock_user_struct(VERIFY_READ, fdesc, haddr, 1)) {
fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), 1);
if (!fdesc) {
goto give_sigsegv;
}
__get_user(dest, fdesc);
__get_user(env->gr[19], fdesc + 1);
unlock_user_struct(fdesc, haddr, 1);
unlock_user(fdesc, haddr, 0);
haddr = dest;
}
env->iaoq_f = haddr;
env->iaoq_b = haddr + 4;
env->psw_n = 0;
return;
give_sigsegv:

BIN
pc-bios/hppa-firmware.img
View File

Binary file not shown.

2
roms/seabios-hppa

@ -1 +1 @@
Subproject commit 673d2595d4f773cc266cbf8dbaf2f475a6adb949
Subproject commit 763e3b73499db5fef94087bd310bfc8ccbcf7858

11
target/hppa/cpu.h
View File

@ -211,8 +211,14 @@ typedef struct CPUArchState {
target_ureg shadow[7]; /* shadow registers */
/* ??? The number of entries isn't specified by the architecture. */
#ifdef TARGET_HPPA64
#define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-bit machines */
#else
#define HPPA_BTLB_FIXED 16
#endif
#define HPPA_BTLB_VARIABLE 0
#define HPPA_TLB_ENTRIES 256
#define HPPA_BTLB_ENTRIES 0
#define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE)
/* ??? Implement a unified itlb/dtlb for the moment. */
/* ??? We should use a more intelligent data structure. */
@ -344,7 +350,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot);
int type, hwaddr *pphys, int *pprot,
hppa_tlb_entry **tlb_entry);
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);

1
target/hppa/helper.h
View File

@ -95,4 +95,5 @@ DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl)
DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_1(diag_btlb, void, env)
#endif

2
target/hppa/insns.decode
View File

@ -528,4 +528,4 @@ fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64
# diag
diag 000101 ----- ----- ---- ---- ---- ----
diag 000101 i:26

2
target/hppa/int_helper.c
View File

@ -154,7 +154,7 @@ void hppa_cpu_do_interrupt(CPUState *cs)
vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr);
t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
0, &paddr, &prot);
0, &paddr, &prot, NULL);
if (t >= 0) {
/* We can't re-load the instruction. */
env->cr[CR_IIR] = 0;

179
target/hppa/mem_helper.c
View File

@ -41,16 +41,24 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
return NULL;
}
static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
bool force_flush_btlb)
{
CPUState *cs = env_cpu(env);
unsigned i, n = 1 << (2 * ent->page_size);
uint64_t addr = ent->va_b;
if (!ent->entry_valid) {
return;
}
trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
tlb_flush_range_by_mmuidx(cs, ent->va_b,
ent->va_e - ent->va_b + 1,
HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS);
/* never clear BTLBs, unless forced to do so. */
if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) {
return;
}
memset(ent, 0, sizeof(*ent));
@ -60,23 +68,35 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env)
{
hppa_tlb_entry *ent;
uint32_t i = env->tlb_last;
uint32_t i;
if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >= ARRAY_SIZE(env->tlb)) {
i = HPPA_BTLB_ENTRIES;
env->tlb_last = HPPA_BTLB_ENTRIES + 1;
} else {
i = env->tlb_last;
env->tlb_last++;
}
env->tlb_last = (i == ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1);
ent = &env->tlb[i];
hppa_flush_tlb_ent(env, ent);
hppa_flush_tlb_ent(env, ent, false);
return ent;
}
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot)
int type, hwaddr *pphys, int *pprot,
hppa_tlb_entry **tlb_entry)
{
hwaddr phys;
int prot, r_prot, w_prot, x_prot, priv;
hppa_tlb_entry *ent;
int ret = -1;
if (tlb_entry) {
*tlb_entry = NULL;
}
/* Virtual translation disabled. Direct map virtual to physical. */
if (mmu_idx == MMU_PHYS_IDX) {
phys = addr;
@ -93,8 +113,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
goto egress;
}
if (tlb_entry) {
*tlb_entry = ent;
}
/* We now know the physical address. */
phys = ent->pa + (addr & ~TARGET_PAGE_MASK);
phys = ent->pa + (addr - ent->va_b);
/* Map TLB access_rights field to QEMU protection. */
priv = MMU_IDX_TO_PRIV(mmu_idx);
@ -193,7 +217,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, 0,
&phys, &prot);
&phys, &prot, NULL);
/* Since we're translating for debugging, the only error that is a
hard error is no translation at all. Otherwise, while a real cpu
@ -207,6 +231,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
hppa_tlb_entry *ent;
int prot, excp, a_prot;
hwaddr phys;
@ -223,7 +248,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
}
excp = hppa_get_physical_address(env, addr, mmu_idx,
a_prot, &phys, &prot);
a_prot, &phys, &prot, &ent);
if (unlikely(excp >= 0)) {
if (probe) {
return false;
@ -243,7 +268,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
phys & TARGET_PAGE_MASK, size, type, mmu_idx);
/* Success! Store the translation into the QEMU TLB. */
tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
prot, mmu_idx, TARGET_PAGE_SIZE << (ent ? 2 * ent->page_size : 0));
return true;
}
@ -254,11 +279,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
int i;
/* Zap any old entries covering ADDR; notice empty entries on the way. */
for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) {
for (i = HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) {
hppa_tlb_entry *ent = &env->tlb[i];
if (ent->va_b <= addr && addr <= ent->va_e) {
if (ent->entry_valid) {
hppa_flush_tlb_ent(env, ent);
hppa_flush_tlb_ent(env, ent, false);
}
if (!empty) {
empty = ent;
@ -278,16 +303,8 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
}
/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg reg)
{
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
if (unlikely(ent == NULL)) {
qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
return;
}
ent->access_id = extract32(reg, 1, 18);
ent->u = extract32(reg, 19, 1);
ent->ar_pl2 = extract32(reg, 20, 2);
@ -301,6 +318,19 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t);
}
/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
{
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
if (unlikely(ent == NULL)) {
qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
return;
}
set_access_bits(env, ent, reg);
}
/* Purge (Insn/Data) TLB. This is explicitly page-based, and is
synchronous across all processors. */
static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
@ -310,7 +340,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
if (ent && ent->entry_valid) {
hppa_flush_tlb_ent(env, ent);
hppa_flush_tlb_ent(env, ent, false);
}
}
@ -334,7 +364,10 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
void HELPER(ptlbe)(CPUHPPAState *env)
{
trace_hppa_tlb_ptlbe(env);
memset(env->tlb, 0, sizeof(env->tlb));
qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n");
memset(&env->tlb[HPPA_BTLB_ENTRIES], 0,
sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0]));
env->tlb_last = HPPA_BTLB_ENTRIES;
tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
@ -356,7 +389,7 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
int prot, excp;
excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0,
&phys, &prot);
&phys, &prot, NULL);
if (excp >= 0) {
if (env->psw & PSW_Q) {
/* ??? Needs tweaking for hppa64. */
@ -379,3 +412,95 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr);
return ent ? ent->ar_type : -1;
}
/*
* diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to
* allow operating systems to modify the Block TLB (BTLB) entries.
* For implementation details see page 1-13 in
* https://parisc.wiki.kernel.org/images-parisc/e/ef/Pdc11-v0.96-Ch1-procs.pdf
*/
void HELPER(diag_btlb)(CPUHPPAState *env)
{
unsigned int phys_page, len, slot;
int mmu_idx = cpu_mmu_index(env, 0);
uintptr_t ra = GETPC();
hppa_tlb_entry *btlb;
uint64_t virt_page;
uint32_t *vaddr;
#ifdef TARGET_HPPA64
/* BTLBs are not supported on 64-bit CPUs */
env->gr[28] = -1; /* nonexistent procedure */
return;
#endif
env->gr[28] = 0; /* PDC_OK */
switch (env->gr[25]) {
case 0:
/* return BTLB parameters */
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INFO\n");
vaddr = probe_access(env, env->gr[24], 4 * sizeof(target_ulong),
MMU_DATA_STORE, mmu_idx, ra);
if (vaddr == NULL) {
env->gr[28] = -10; /* invalid argument */
} else {
vaddr[0] = cpu_to_be32(1);
vaddr[1] = cpu_to_be32(16 * 1024);
vaddr[2] = cpu_to_be32(HPPA_BTLB_FIXED);
vaddr[3] = cpu_to_be32(HPPA_BTLB_VARIABLE);
}
break;
case 1:
/* insert BTLB entry */
virt_page = env->gr[24]; /* upper 32 bits */
virt_page <<= 32;
virt_page |= env->gr[23]; /* lower 32 bits */
phys_page = env->gr[22];
len = env->gr[21];
slot = env->gr[19];
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INSERT "
"0x%08llx-0x%08llx: vpage 0x%llx for phys page 0x%04x len %d "
"into slot %d\n",
(long long) virt_page << TARGET_PAGE_BITS,
(long long) (virt_page + len) << TARGET_PAGE_BITS,
(long long) virt_page, phys_page, len, slot);
if (slot < HPPA_BTLB_ENTRIES) {
btlb = &env->tlb[slot];
/* force flush of possibly existing BTLB entry */
hppa_flush_tlb_ent(env, btlb, true);
/* create new BTLB entry */
btlb->va_b = virt_page << TARGET_PAGE_BITS;
btlb->va_e = btlb->va_b + len * TARGET_PAGE_SIZE - 1;
btlb->pa = phys_page << TARGET_PAGE_BITS;
set_access_bits(env, btlb, env->gr[20]);
btlb->t = 0;
btlb->d = 1;
} else {
env->gr[28] = -10; /* invalid argument */
}
break;
case 2:
/* Purge BTLB entry */
slot = env->gr[22];
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n",
slot);
if (slot < HPPA_BTLB_ENTRIES) {
btlb = &env->tlb[slot];
hppa_flush_tlb_ent(env, btlb, true);
} else {
env->gr[28] = -10; /* invalid argument */
}
break;
case 3:
/* Purge all BTLB entries */
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n");
for (slot = 0; slot < HPPA_BTLB_ENTRIES; slot++) {
btlb = &env->tlb[slot];
hppa_flush_tlb_ent(env, btlb, true);
}
break;
default:
env->gr[28] = -2; /* nonexistent option */
break;
}
}

3
target/hppa/op_helper.c
View File

@ -179,7 +179,8 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
return 0;
}
excp = hppa_get_physical_address(env, addr, level, 0, &phys, &prot);
excp = hppa_get_physical_address(env, addr, level, 0, &phys,
&prot, NULL);
if (excp >= 0) {
if (env->psw & PSW_Q) {
/* ??? Needs tweaking for hppa64. */

15
target/hppa/translate.c
View File

@ -4042,9 +4042,18 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a)
static bool trans_diag(DisasContext *ctx, arg_diag *a)
{
qemu_log_mask(LOG_UNIMP, "DIAG opcode ignored\n");
cond_free(&ctx->null_cond);
return true;
nullify_over(ctx);
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
if (a->i == 0x100) {
/* emulate PDC BTLB, called by SeaBIOS-hppa */
gen_helper_diag_btlb(cpu_env);
} else
#endif
{
qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
}
return nullify_end(ctx);
}
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)