mirror of https://github.com/proxmox/mirror_qemu
target/riscv/cpu.c: limit cfg->vext_spec log message
Inside riscv_cpu_validate_v() we're always throwing a log message if the user didn't set a vector version via 'vext_spec'. We're going to include one case with the 'max' CPU where env->vext_ver will be set in the cpu_init(). But that alone will not stop the "vector version is not specified" message from appearing. The usefulness of this log message is debatable for the generic CPUs, but for a 'max' CPU type, where we are supposed to deliver a CPU model with all features possible, it's strange to force users to set 'vext_spec' to get rid of this message. Change riscv_cpu_validate_v() to not throw this log message if env->vext_ver is already set. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230912132423.268494-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
parent
b55c39b3f5
commit
cbaac1d22b
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@ -959,8 +959,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
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Error **errp)
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{
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int vext_version = VEXT_VERSION_1_00_0;
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if (!is_power_of_2(cfg->vlen)) {
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error_setg(errp, "Vector extension VLEN must be power of 2");
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return;
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@ -983,17 +981,18 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
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}
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if (cfg->vext_spec) {
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if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
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vext_version = VEXT_VERSION_1_00_0;
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env->vext_ver = VEXT_VERSION_1_00_0;
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} else {
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error_setg(errp, "Unsupported vector spec version '%s'",
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cfg->vext_spec);
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return;
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}
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} else {
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} else if (env->vext_ver == 0) {
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qemu_log("vector version is not specified, "
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"use the default value v1.0\n");
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env->vext_ver = VEXT_VERSION_1_00_0;
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}
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env->vext_ver = vext_version;
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}
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static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
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