usb/hcd-ehci: Replace PORTSC macros with variables

Replace PORTSC macros with variables which could then be
configured in ehci_xxxx_class_init(...)

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
master
Kuo-Jung Su 2013-06-06 15:41:12 +02:00 committed by Gerd Hoffmann
parent 20c570432e
commit cc8d6a8481
4 changed files with 28 additions and 14 deletions

View File

@ -78,6 +78,8 @@ static void usb_ehci_pci_init(Object *obj)
s->capsbase = 0x00; s->capsbase = 0x00;
s->opregbase = 0x20; s->opregbase = 0x20;
s->portscbase = 0x44;
s->portnr = NB_PORTS;
usb_ehci_init(s, DEVICE(obj)); usb_ehci_init(s, DEVICE(obj));
} }

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@ -51,6 +51,8 @@ static void ehci_sysbus_init(Object *obj)
s->capsbase = sec->capsbase; s->capsbase = sec->capsbase;
s->opregbase = sec->opregbase; s->opregbase = sec->opregbase;
s->portscbase = sec->portscbase;
s->portnr = sec->portnr;
s->as = &address_space_memory; s->as = &address_space_memory;
usb_ehci_init(s, DEVICE(obj)); usb_ehci_init(s, DEVICE(obj));
@ -60,6 +62,10 @@ static void ehci_sysbus_init(Object *obj)
static void ehci_sysbus_class_init(ObjectClass *klass, void *data) static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
sec->portscbase = 0x44;
sec->portnr = NB_PORTS;
dc->realize = usb_ehci_sysbus_realize; dc->realize = usb_ehci_sysbus_realize;
dc->vmsd = &vmstate_ehci_sysbus; dc->vmsd = &vmstate_ehci_sysbus;

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@ -995,7 +995,7 @@ static uint64_t ehci_port_read(void *ptr, hwaddr addr,
uint32_t val; uint32_t val;
val = s->portsc[addr >> 2]; val = s->portsc[addr >> 2];
trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val); trace_usb_ehci_portsc_read(addr + s->portscbase, addr >> 2, val);
return val; return val;
} }
@ -1036,7 +1036,7 @@ static void ehci_port_write(void *ptr, hwaddr addr,
uint32_t old = *portsc; uint32_t old = *portsc;
USBDevice *dev = s->ports[port].dev; USBDevice *dev = s->ports[port].dev;
trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val); trace_usb_ehci_portsc_write(addr + s->portscbase, addr >> 2, val);
/* Clear rwc bits */ /* Clear rwc bits */
*portsc &= ~(val & PORTSC_RWC_MASK); *portsc &= ~(val & PORTSC_RWC_MASK);
@ -1069,7 +1069,7 @@ static void ehci_port_write(void *ptr, hwaddr addr,
*portsc &= ~PORTSC_RO_MASK; *portsc &= ~PORTSC_RO_MASK;
*portsc |= val; *portsc |= val;
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old); trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old);
} }
static void ehci_opreg_write(void *ptr, hwaddr addr, static void ehci_opreg_write(void *ptr, hwaddr addr,
@ -2512,8 +2512,14 @@ void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
{ {
int i; int i;
if (s->portnr > NB_PORTS) {
error_setg(errp, "Too many ports! Max. port number is %d.",
NB_PORTS);
return;
}
usb_bus_new(&s->bus, &ehci_bus_ops, dev); usb_bus_new(&s->bus, &ehci_bus_ops, dev);
for (i = 0; i < NB_PORTS; i++) { for (i = 0; i < s->portnr; i++) {
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
USB_SPEED_MASK_HIGH); USB_SPEED_MASK_HIGH);
s->ports[i].dev = 0; s->ports[i].dev = 0;
@ -2533,7 +2539,7 @@ void usb_ehci_init(EHCIState *s, DeviceState *dev)
s->caps[0x01] = 0x00; s->caps[0x01] = 0x00;
s->caps[0x02] = 0x00; s->caps[0x02] = 0x00;
s->caps[0x03] = 0x01; /* HC version */ s->caps[0x03] = 0x01; /* HC version */
s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ s->caps[0x04] = s->portnr; /* Number of downstream ports */
s->caps[0x05] = 0x00; /* No companion ports at present */ s->caps[0x05] = 0x00; /* No companion ports at present */
s->caps[0x06] = 0x00; s->caps[0x06] = 0x00;
s->caps[0x07] = 0x00; s->caps[0x07] = 0x00;
@ -2549,13 +2555,13 @@ void usb_ehci_init(EHCIState *s, DeviceState *dev)
memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s,
"capabilities", CAPA_SIZE); "capabilities", CAPA_SIZE);
memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s,
"operational", PORTSC_BEGIN); "operational", s->portscbase);
memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s,
"ports", PORTSC_END - PORTSC_BEGIN); "ports", 4 * s->portnr);
memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase,
&s->mem_ports); &s->mem_ports);
} }

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@ -40,11 +40,7 @@
#define MMIO_SIZE 0x1000 #define MMIO_SIZE 0x1000
#define CAPA_SIZE 0x10 #define CAPA_SIZE 0x10
#define PORTSC 0x0044 #define NB_PORTS 6 /* Max. Number of downstream ports */
#define PORTSC_BEGIN PORTSC
#define PORTSC_END (PORTSC + 4 * NB_PORTS)
#define NB_PORTS 6 /* Number of downstream ports */
typedef struct EHCIPacket EHCIPacket; typedef struct EHCIPacket EHCIPacket;
typedef struct EHCIQueue EHCIQueue; typedef struct EHCIQueue EHCIQueue;
@ -268,6 +264,8 @@ struct EHCIState {
int companion_count; int companion_count;
uint16_t capsbase; uint16_t capsbase;
uint16_t opregbase; uint16_t opregbase;
uint16_t portscbase;
uint16_t portnr;
/* properties */ /* properties */
uint32_t maxframes; uint32_t maxframes;
@ -278,7 +276,7 @@ struct EHCIState {
*/ */
uint8_t caps[CAPA_SIZE]; uint8_t caps[CAPA_SIZE];
union { union {
uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)]; uint32_t opreg[0x44/sizeof(uint32_t)];
struct { struct {
uint32_t usbcmd; uint32_t usbcmd;
uint32_t usbsts; uint32_t usbsts;
@ -363,6 +361,8 @@ typedef struct SysBusEHCIClass {
uint16_t capsbase; uint16_t capsbase;
uint16_t opregbase; uint16_t opregbase;
uint16_t portscbase;
uint16_t portnr;
} SysBusEHCIClass; } SysBusEHCIClass;
#endif #endif