mirror of https://github.com/proxmox/mirror_qemu
x86: Support XFD and AMX xsave data migration
XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily. Signed-off-by: Zeng Guang <guang.zeng@intel.com> Signed-off-by: Wei Wang <wei.w.wang@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20220217060434.52460-8-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>master
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e56dd3c70a
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cdec2b753b
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@ -507,6 +507,9 @@ typedef enum X86Seg {
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#define MSR_VM_HSAVE_PA 0xc0010117
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#define MSR_VM_HSAVE_PA 0xc0010117
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#define MSR_IA32_XFD 0x000001c4
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#define MSR_IA32_XFD_ERR 0x000001c5
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define MSR_IA32_XSS 0x00000da0
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#define MSR_IA32_XSS 0x00000da0
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#define MSR_IA32_UMWAIT_CONTROL 0xe1
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#define MSR_IA32_UMWAIT_CONTROL 0xe1
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@ -872,6 +875,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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/* AVX512 BFloat16 Instruction */
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/* AVX512 BFloat16 Instruction */
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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/* XFD Extend Feature Disabled */
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#define CPUID_D_1_EAX_XFD (1U << 4)
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/* Packets which contain IP payload have LIP values */
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/* Packets which contain IP payload have LIP values */
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#define CPUID_14_0_ECX_LIP (1U << 31)
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#define CPUID_14_0_ECX_LIP (1U << 31)
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@ -1616,6 +1621,10 @@ typedef struct CPUArchState {
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uint64_t msr_rtit_cr3_match;
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uint64_t msr_rtit_cr3_match;
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uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
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uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
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/* Per-VCPU XFD MSRs */
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uint64_t msr_xfd;
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uint64_t msr_xfd_err;
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/* exception/interrupt handling */
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/* exception/interrupt handling */
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int error_code;
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int error_code;
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int exception_is_int;
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int exception_is_int;
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@ -3277,6 +3277,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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env->msr_ia32_sgxlepubkeyhash[3]);
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env->msr_ia32_sgxlepubkeyhash[3]);
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}
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}
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if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
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kvm_msr_entry_add(cpu, MSR_IA32_XFD,
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env->msr_xfd);
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kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
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env->msr_xfd_err);
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}
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/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
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/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
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* kvm_put_msr_feature_control. */
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* kvm_put_msr_feature_control. */
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}
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}
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@ -3669,6 +3676,11 @@ static int kvm_get_msrs(X86CPU *cpu)
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kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
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}
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}
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if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
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kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
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}
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ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
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ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
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if (ret < 0) {
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if (ret < 0) {
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return ret;
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return ret;
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@ -3965,6 +3977,12 @@ static int kvm_get_msrs(X86CPU *cpu)
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env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
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env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
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msrs[i].data;
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msrs[i].data;
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break;
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break;
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case MSR_IA32_XFD:
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env->msr_xfd = msrs[i].data;
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break;
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case MSR_IA32_XFD_ERR:
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env->msr_xfd_err = msrs[i].data;
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break;
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}
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}
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}
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}
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@ -1483,6 +1483,48 @@ static const VMStateDescription vmstate_pdptrs = {
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}
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}
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};
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};
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static bool xfd_msrs_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD);
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}
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static const VMStateDescription vmstate_msr_xfd = {
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.name = "cpu/msr_xfd",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = xfd_msrs_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(env.msr_xfd, X86CPU),
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VMSTATE_UINT64(env.msr_xfd_err, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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#ifdef TARGET_X86_64
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static bool amx_xtile_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE);
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}
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static const VMStateDescription vmstate_amx_xtile = {
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.name = "cpu/intel_amx_xtile",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = amx_xtile_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64),
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VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192),
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VMSTATE_END_OF_LIST()
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}
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};
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#endif
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const VMStateDescription vmstate_x86_cpu = {
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const VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.name = "cpu",
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.version_id = 12,
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.version_id = 12,
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@ -1622,6 +1664,10 @@ const VMStateDescription vmstate_x86_cpu = {
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&vmstate_msr_tsx_ctrl,
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&vmstate_msr_tsx_ctrl,
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&vmstate_msr_intel_sgx,
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&vmstate_msr_intel_sgx,
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&vmstate_pdptrs,
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&vmstate_pdptrs,
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&vmstate_msr_xfd,
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#ifdef TARGET_X86_64
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&vmstate_amx_xtile,
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#endif
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NULL
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NULL
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}
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}
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};
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};
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