mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: Implement store-exclusive for system mode
System mode store-exclusive use a different code path to usermode ones; implement this missing code, in a similar way to the 32 bit version. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>master
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7900e9f1f9
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d324b36ad9
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@ -1487,12 +1487,68 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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}
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}
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#else
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#else
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i64 addr, int size, int is_pair)
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TCGv_i64 inaddr, int size, int is_pair)
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{
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{
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qemu_log_mask(LOG_UNIMP,
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/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
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"%s:%d: system mode store_exclusive unsupported "
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* && (!is_pair || env->exclusive_high == [addr + datasize])) {
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"at pc=%016" PRIx64 "\n",
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* [addr] = {Rt};
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__FILE__, __LINE__, s->pc - 4);
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* if (is_pair) {
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* [addr + datasize] = {Rt2};
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* }
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* {Rd} = 0;
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* } else {
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* {Rd} = 1;
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* }
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* env->exclusive_addr = -1;
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*/
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int fail_label = gen_new_label();
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int done_label = gen_new_label();
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TCGv_i64 addr = tcg_temp_local_new_i64();
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TCGv_i64 tmp;
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/* Copy input into a local temp so it is not trashed when the
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* basic block ends at the branch insn.
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*/
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tcg_gen_mov_i64(addr, inaddr);
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tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
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tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
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tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
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tcg_temp_free_i64(tmp);
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if (is_pair) {
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TCGv_i64 addrhi = tcg_temp_new_i64();
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TCGv_i64 tmphi = tcg_temp_new_i64();
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tcg_gen_addi_i64(addrhi, addr, 1 << size);
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tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
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tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
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tcg_temp_free_i64(tmphi);
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tcg_temp_free_i64(addrhi);
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}
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/* We seem to still have the exclusive monitor, so do the store */
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tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
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if (is_pair) {
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TCGv_i64 addrhi = tcg_temp_new_i64();
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tcg_gen_addi_i64(addrhi, addr, 1 << size);
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tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
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get_mem_index(s), MO_TE + size);
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tcg_temp_free_i64(addrhi);
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}
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tcg_temp_free_i64(addr);
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tcg_gen_movi_i64(cpu_reg(s, rd), 0);
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tcg_gen_br(done_label);
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gen_set_label(fail_label);
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tcg_gen_movi_i64(cpu_reg(s, rd), 1);
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gen_set_label(done_label);
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tcg_gen_movi_i64(cpu_exclusive_addr, -1);
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}
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}
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#endif
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#endif
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