mirror of https://github.com/proxmox/mirror_qemu
target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()
Use arm_dc_feature() rather than arm_feature() to avoid using CPUARMState unnecessarily. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1414524244-20316-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>master
Peter Maydell
parent
2b51668fca
commit
d614a51378
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@ -2619,7 +2619,7 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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#define VFP_SREG(insn, bigbit, smallbit) \
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((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
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#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
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if (arm_feature(env, ARM_FEATURE_VFP3)) { \
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if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
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reg = (((insn) >> (bigbit)) & 0x0f) \
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| (((insn) >> ((smallbit) - 4)) & 0x10); \
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} else { \
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@ -2970,7 +2970,7 @@ static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
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if (!arm_feature(env, ARM_FEATURE_V8)) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return 1;
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}
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@ -3010,8 +3010,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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if (!arm_feature(env, ARM_FEATURE_VFP))
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if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
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return 1;
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}
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/* FIXME: this access check should not take precedence over UNDEF
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* for invalid encodings; we will generate incorrect syndrome information
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@ -3055,8 +3056,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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if (insn & 0xf)
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return 1;
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if (insn & 0x00c00060
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&& !arm_feature(env, ARM_FEATURE_NEON))
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&& !arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return 1;
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}
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pass = (insn >> 21) & 1;
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if (insn & (1 << 22)) {
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@ -3151,8 +3153,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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VFP3 restricts all id registers to privileged
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accesses. */
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if (IS_USER(s)
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&& arm_feature(env, ARM_FEATURE_VFP3))
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&& arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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case ARM_VFP_FPEXC:
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@ -3164,8 +3167,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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case ARM_VFP_FPINST2:
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/* Not present in VFP3. */
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if (IS_USER(s)
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|| arm_feature(env, ARM_FEATURE_VFP3))
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|| arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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case ARM_VFP_FPSCR:
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@ -3178,15 +3182,16 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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}
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break;
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case ARM_VFP_MVFR2:
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if (!arm_feature(env, ARM_FEATURE_V8)) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return 1;
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}
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/* fall through */
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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if (IS_USER(s)
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|| !arm_feature(env, ARM_FEATURE_MVFR))
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|| !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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default:
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@ -3367,8 +3372,8 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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* UNPREDICTABLE if bit 8 is set prior to ARMv8
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* (we choose to UNDEF)
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*/
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if ((dp && !arm_feature(env, ARM_FEATURE_V8)) ||
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!arm_feature(env, ARM_FEATURE_VFP_FP16)) {
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if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
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!arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
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return 1;
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}
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if (!extract32(rn, 1, 1)) {
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@ -3447,7 +3452,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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* correct : an input NaN should come out with its sign bit
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* flipped if it is a negated-input.
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*/
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if (!arm_feature(env, ARM_FEATURE_VFP4)) {
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if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
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return 1;
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}
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if (dp) {
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@ -3488,8 +3493,9 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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}
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break;
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case 14: /* fconst */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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n = (insn << 12) & 0x80000000;
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i = ((insn >> 12) & 0x70) | (insn & 0xf);
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@ -3644,23 +3650,27 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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gen_vfp_sito(dp, 0);
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break;
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case 20: /* fshto */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_shto(dp, 16 - rm, 0);
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break;
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case 21: /* fslto */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_slto(dp, 32 - rm, 0);
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break;
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case 22: /* fuhto */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_uhto(dp, 16 - rm, 0);
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break;
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case 23: /* fulto */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_ulto(dp, 32 - rm, 0);
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break;
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case 24: /* ftoui */
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@ -3676,23 +3686,27 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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gen_vfp_tosiz(dp, 0);
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break;
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case 28: /* ftosh */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_tosh(dp, 16 - rm, 0);
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break;
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case 29: /* ftosl */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_tosl(dp, 32 - rm, 0);
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break;
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case 30: /* ftouh */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_touh(dp, 16 - rm, 0);
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break;
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case 31: /* ftoul */
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if (!arm_feature(env, ARM_FEATURE_VFP3))
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return 1;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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gen_vfp_toul(dp, 32 - rm, 0);
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break;
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default: /* undefined */
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@ -3963,14 +3977,18 @@ static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr)
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/* Mask out undefined bits. */
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mask &= ~CPSR_RESERVED;
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if (!arm_feature(env, ARM_FEATURE_V4T))
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if (!arm_dc_feature(s, ARM_FEATURE_V4T)) {
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mask &= ~CPSR_T;
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if (!arm_feature(env, ARM_FEATURE_V5))
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}
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if (!arm_dc_feature(s, ARM_FEATURE_V5)) {
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mask &= ~CPSR_Q; /* V5TE in reality*/
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if (!arm_feature(env, ARM_FEATURE_V6))
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}
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if (!arm_dc_feature(s, ARM_FEATURE_V6)) {
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mask &= ~(CPSR_E | CPSR_GE);
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if (!arm_feature(env, ARM_FEATURE_THUMB2))
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}
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if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
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mask &= ~CPSR_IT;
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}
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/* Mask out execution state and reserved bits. */
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if (!spsr) {
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mask &= ~(CPSR_EXEC | CPSR_RESERVED);
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@ -5092,7 +5110,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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return 1;
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}
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if (!u) { /* SHA-1 */
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if (!arm_feature(env, ARM_FEATURE_V8_SHA1)) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
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return 1;
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}
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tmp = tcg_const_i32(rd);
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@ -5102,7 +5120,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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gen_helper_crypto_sha1_3reg(cpu_env, tmp, tmp2, tmp3, tmp4);
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tcg_temp_free_i32(tmp4);
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} else { /* SHA-256 */
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if (!arm_feature(env, ARM_FEATURE_V8_SHA256) || size == 3) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size == 3) {
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return 1;
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}
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tmp = tcg_const_i32(rd);
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@ -5237,7 +5255,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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break;
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case NEON_3R_FLOAT_MISC:
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/* VMAXNM/VMINNM in ARMv8 */
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if (u && !arm_feature(env, ARM_FEATURE_V8)) {
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if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) {
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return 1;
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}
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break;
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@ -5248,7 +5266,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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}
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break;
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case NEON_3R_VFM:
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if (!arm_feature(env, ARM_FEATURE_VFP4) || u) {
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if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) {
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return 1;
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}
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break;
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@ -6067,7 +6085,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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if (op == 14 && size == 2) {
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TCGv_i64 tcg_rn, tcg_rm, tcg_rd;
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if (!arm_feature(env, ARM_FEATURE_V8_PMULL)) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
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return 1;
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}
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tcg_rn = tcg_temp_new_i64();
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@ -6555,7 +6573,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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}
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break;
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case NEON_2RM_VCVT_F16_F32:
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
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if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
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q || (rm & 1)) {
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return 1;
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}
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@ -6579,7 +6597,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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tcg_temp_free_i32(tmp);
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break;
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case NEON_2RM_VCVT_F32_F16:
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if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
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if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
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q || (rd & 1)) {
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return 1;
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}
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@ -6603,7 +6621,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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tcg_temp_free_i32(tmp3);
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break;
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case NEON_2RM_AESE: case NEON_2RM_AESMC:
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if (!arm_feature(env, ARM_FEATURE_V8_AES)
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if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
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|| ((rm | rd) & 1)) {
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return 1;
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}
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@ -6625,7 +6643,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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tcg_temp_free_i32(tmp3);
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break;
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case NEON_2RM_SHA1H:
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if (!arm_feature(env, ARM_FEATURE_V8_SHA1)
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if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)
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|| ((rm | rd) & 1)) {
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return 1;
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}
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@ -6643,10 +6661,10 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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}
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/* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
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if (q) {
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if (!arm_feature(env, ARM_FEATURE_V8_SHA256)) {
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if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256)) {
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return 1;
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}
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} else if (!arm_feature(env, ARM_FEATURE_V8_SHA1)) {
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} else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
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return 1;
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}
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tmp = tcg_const_i32(rd);
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@ -7039,13 +7057,13 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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cpnum = (insn >> 8) & 0xf;
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/* First check for coprocessor space used for XScale/iwMMXt insns */
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if (arm_feature(env, ARM_FEATURE_XSCALE) && (cpnum < 2)) {
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if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) {
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if (extract32(s->c15_cpar, cpnum, 1) == 0) {
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return 1;
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}
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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return disas_iwmmxt_insn(env, s, insn);
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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} else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) {
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return disas_dsp_insn(env, s, insn);
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}
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return 1;
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@ -7082,7 +7100,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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}
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if (ri->accessfn ||
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(arm_feature(env, ARM_FEATURE_XSCALE) && cpnum < 14)) {
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(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
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/* Emit code to perform further access permissions checks at
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* runtime; this may result in an exception.
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* Note that on XScale all cp0..c13 registers do an access check
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@ -7125,7 +7143,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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* in which case the syndrome information won't actually be
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* guest visible.
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*/
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assert(!arm_feature(env, ARM_FEATURE_V8));
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assert(!arm_dc_feature(s, ARM_FEATURE_V8));
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syndrome = syn_uncategorized();
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break;
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}
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@ -7569,8 +7587,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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/* Unconditional instructions. */
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if (((insn >> 25) & 7) == 1) {
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/* NEON Data processing. */
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if (!arm_feature(env, ARM_FEATURE_NEON))
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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goto illegal_op;
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}
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if (disas_neon_data_insn(env, s, insn))
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goto illegal_op;
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@ -7578,8 +7597,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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}
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if ((insn & 0x0f100000) == 0x04000000) {
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/* NEON load/store. */
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if (!arm_feature(env, ARM_FEATURE_NEON))
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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goto illegal_op;
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}
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if (disas_neon_ls_insn(env, s, insn))
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goto illegal_op;
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@ -7596,7 +7616,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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((insn & 0x0f30f010) == 0x0710f000)) {
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if ((insn & (1 << 22)) == 0) {
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/* PLDW; v7MP */
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if (!arm_feature(env, ARM_FEATURE_V7MP)) {
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
}
|
||||
|
|
@ -7611,7 +7631,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||
}
|
||||
if (((insn & 0x0f700000) == 0x04100000) ||
|
||||
((insn & 0x0f700010) == 0x06100000)) {
|
||||
if (!arm_feature(env, ARM_FEATURE_V7MP)) {
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
return; /* v7MP: Unallocated memory hint: must NOP */
|
||||
|
|
@ -7708,7 +7728,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||
gen_bx_im(s, val);
|
||||
return;
|
||||
} else if ((insn & 0x0e000f00) == 0x0c000100) {
|
||||
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
||||
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
|
||||
/* iWMMXt register transfer. */
|
||||
if (extract32(s->c15_cpar, 1, 1)) {
|
||||
if (!disas_iwmmxt_insn(env, s, insn)) {
|
||||
|
|
@ -7864,7 +7884,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||
* op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
|
||||
* Bits 8, 10 and 11 should be zero.
|
||||
*/
|
||||
if (!arm_feature(env, ARM_FEATURE_CRC) || op1 == 0x3 ||
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_CRC) || op1 == 0x3 ||
|
||||
(c & 0xd) != 0) {
|
||||
goto illegal_op;
|
||||
}
|
||||
|
|
@ -8673,7 +8693,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
|||
case 1:
|
||||
case 3:
|
||||
/* SDIV, UDIV */
|
||||
if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_ARM_DIV)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
if (((insn >> 5) & 7) || (rd != 15)) {
|
||||
|
|
@ -9069,8 +9089,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||
int conds;
|
||||
int logic_cc;
|
||||
|
||||
if (!(arm_feature(env, ARM_FEATURE_THUMB2)
|
||||
|| arm_feature (env, ARM_FEATURE_M))) {
|
||||
if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
|
||||
|| arm_dc_feature(s, ARM_FEATURE_M))) {
|
||||
/* Thumb-1 cores may need to treat bl and blx as a pair of
|
||||
16-bit instructions to get correct prefetch abort behavior. */
|
||||
insn = insn_hw1;
|
||||
|
|
@ -9523,7 +9543,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||
uint32_t sz = op & 0x3;
|
||||
uint32_t c = op & 0x8;
|
||||
|
||||
if (!arm_feature(env, ARM_FEATURE_CRC)) {
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_CRC)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
|
||||
|
|
@ -9651,7 +9671,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
|
|||
tmp2 = load_reg(s, rm);
|
||||
if ((op & 0x50) == 0x10) {
|
||||
/* sdiv, udiv */
|
||||
if (!arm_feature(env, ARM_FEATURE_THUMB_DIV)) {
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DIV)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
if (op & 0x20)
|
||||
|
|
|
|||
Loading…
Reference in New Issue