mirror of https://github.com/proxmox/mirror_qemu
target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also give the correct answers where the inline implementation did not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>master
Peter Maydell
Aurelien Jarno
parent
02acedf93d
commit
d68a6f3a6d
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@ -466,5 +466,10 @@ DEF_HELPER_3(neon_unzip16, void, env, i32, i32)
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DEF_HELPER_3(neon_qunzip8, void, env, i32, i32)
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DEF_HELPER_3(neon_qunzip16, void, env, i32, i32)
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DEF_HELPER_3(neon_qunzip32, void, env, i32, i32)
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DEF_HELPER_3(neon_zip8, void, env, i32, i32)
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DEF_HELPER_3(neon_zip16, void, env, i32, i32)
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DEF_HELPER_3(neon_qzip8, void, env, i32, i32)
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DEF_HELPER_3(neon_qzip16, void, env, i32, i32)
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DEF_HELPER_3(neon_qzip32, void, env, i32, i32)
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#include "def-helper.h"
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@ -1787,3 +1787,95 @@ void HELPER(neon_unzip16)(CPUState *env, uint32_t rd, uint32_t rm)
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rd] = make_float64(d0);
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}
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void HELPER(neon_qzip8)(CPUState *env, uint32_t rd, uint32_t rm)
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{
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uint64_t zm0 = float64_val(env->vfp.regs[rm]);
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uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
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uint64_t zd0 = float64_val(env->vfp.regs[rd]);
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uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]);
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uint64_t d0 = ELEM(zd0, 0, 8) | (ELEM(zm0, 0, 8) << 8)
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| (ELEM(zd0, 1, 8) << 16) | (ELEM(zm0, 1, 8) << 24)
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| (ELEM(zd0, 2, 8) << 32) | (ELEM(zm0, 2, 8) << 40)
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| (ELEM(zd0, 3, 8) << 48) | (ELEM(zm0, 3, 8) << 56);
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uint64_t d1 = ELEM(zd0, 4, 8) | (ELEM(zm0, 4, 8) << 8)
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| (ELEM(zd0, 5, 8) << 16) | (ELEM(zm0, 5, 8) << 24)
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| (ELEM(zd0, 6, 8) << 32) | (ELEM(zm0, 6, 8) << 40)
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| (ELEM(zd0, 7, 8) << 48) | (ELEM(zm0, 7, 8) << 56);
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uint64_t m0 = ELEM(zd1, 0, 8) | (ELEM(zm1, 0, 8) << 8)
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| (ELEM(zd1, 1, 8) << 16) | (ELEM(zm1, 1, 8) << 24)
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| (ELEM(zd1, 2, 8) << 32) | (ELEM(zm1, 2, 8) << 40)
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| (ELEM(zd1, 3, 8) << 48) | (ELEM(zm1, 3, 8) << 56);
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uint64_t m1 = ELEM(zd1, 4, 8) | (ELEM(zm1, 4, 8) << 8)
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| (ELEM(zd1, 5, 8) << 16) | (ELEM(zm1, 5, 8) << 24)
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| (ELEM(zd1, 6, 8) << 32) | (ELEM(zm1, 6, 8) << 40)
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| (ELEM(zd1, 7, 8) << 48) | (ELEM(zm1, 7, 8) << 56);
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rm + 1] = make_float64(m1);
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env->vfp.regs[rd] = make_float64(d0);
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env->vfp.regs[rd + 1] = make_float64(d1);
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}
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void HELPER(neon_qzip16)(CPUState *env, uint32_t rd, uint32_t rm)
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{
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uint64_t zm0 = float64_val(env->vfp.regs[rm]);
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uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
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uint64_t zd0 = float64_val(env->vfp.regs[rd]);
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uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]);
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uint64_t d0 = ELEM(zd0, 0, 16) | (ELEM(zm0, 0, 16) << 16)
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| (ELEM(zd0, 1, 16) << 32) | (ELEM(zm0, 1, 16) << 48);
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uint64_t d1 = ELEM(zd0, 2, 16) | (ELEM(zm0, 2, 16) << 16)
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| (ELEM(zd0, 3, 16) << 32) | (ELEM(zm0, 3, 16) << 48);
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uint64_t m0 = ELEM(zd1, 0, 16) | (ELEM(zm1, 0, 16) << 16)
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| (ELEM(zd1, 1, 16) << 32) | (ELEM(zm1, 1, 16) << 48);
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uint64_t m1 = ELEM(zd1, 2, 16) | (ELEM(zm1, 2, 16) << 16)
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| (ELEM(zd1, 3, 16) << 32) | (ELEM(zm1, 3, 16) << 48);
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rm + 1] = make_float64(m1);
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env->vfp.regs[rd] = make_float64(d0);
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env->vfp.regs[rd + 1] = make_float64(d1);
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}
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void HELPER(neon_qzip32)(CPUState *env, uint32_t rd, uint32_t rm)
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{
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uint64_t zm0 = float64_val(env->vfp.regs[rm]);
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uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
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uint64_t zd0 = float64_val(env->vfp.regs[rd]);
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uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]);
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uint64_t d0 = ELEM(zd0, 0, 32) | (ELEM(zm0, 0, 32) << 32);
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uint64_t d1 = ELEM(zd0, 1, 32) | (ELEM(zm0, 1, 32) << 32);
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uint64_t m0 = ELEM(zd1, 0, 32) | (ELEM(zm1, 0, 32) << 32);
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uint64_t m1 = ELEM(zd1, 1, 32) | (ELEM(zm1, 1, 32) << 32);
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rm + 1] = make_float64(m1);
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env->vfp.regs[rd] = make_float64(d0);
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env->vfp.regs[rd + 1] = make_float64(d1);
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}
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void HELPER(neon_zip8)(CPUState *env, uint32_t rd, uint32_t rm)
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{
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uint64_t zm = float64_val(env->vfp.regs[rm]);
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uint64_t zd = float64_val(env->vfp.regs[rd]);
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uint64_t d0 = ELEM(zd, 0, 8) | (ELEM(zm, 0, 8) << 8)
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| (ELEM(zd, 1, 8) << 16) | (ELEM(zm, 1, 8) << 24)
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| (ELEM(zd, 2, 8) << 32) | (ELEM(zm, 2, 8) << 40)
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| (ELEM(zd, 3, 8) << 48) | (ELEM(zm, 3, 8) << 56);
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uint64_t m0 = ELEM(zd, 4, 8) | (ELEM(zm, 4, 8) << 8)
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| (ELEM(zd, 5, 8) << 16) | (ELEM(zm, 5, 8) << 24)
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| (ELEM(zd, 6, 8) << 32) | (ELEM(zm, 6, 8) << 40)
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| (ELEM(zd, 7, 8) << 48) | (ELEM(zm, 7, 8) << 56);
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rd] = make_float64(d0);
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}
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void HELPER(neon_zip16)(CPUState *env, uint32_t rd, uint32_t rm)
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{
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uint64_t zm = float64_val(env->vfp.regs[rm]);
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uint64_t zd = float64_val(env->vfp.regs[rd]);
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uint64_t d0 = ELEM(zd, 0, 16) | (ELEM(zm, 0, 16) << 16)
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| (ELEM(zd, 1, 16) << 32) | (ELEM(zm, 1, 16) << 48);
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uint64_t m0 = ELEM(zd, 2, 16) | (ELEM(zm, 2, 16) << 16)
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| (ELEM(zd, 3, 16) << 32) | (ELEM(zm, 3, 16) << 48);
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env->vfp.regs[rm] = make_float64(m0);
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env->vfp.regs[rd] = make_float64(d0);
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}
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@ -3653,59 +3653,43 @@ static int gen_neon_unzip(int rd, int rm, int size, int q)
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return 0;
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}
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static void gen_neon_zip_u8(TCGv t0, TCGv t1)
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{
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TCGv rd, rm, tmp;
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rd = new_tmp();
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rm = new_tmp();
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tmp = new_tmp();
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tcg_gen_andi_i32(rd, t0, 0xff);
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tcg_gen_shli_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t0, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shli_i32(tmp, t1, 24);
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tcg_gen_andi_i32(tmp, tmp, 0xff000000);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_andi_i32(rm, t1, 0xff000000);
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tcg_gen_shri_i32(tmp, t0, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff0000);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_shri_i32(tmp, t1, 8);
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tcg_gen_andi_i32(tmp, tmp, 0xff00);
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tcg_gen_or_i32(rm, rm, tmp);
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tcg_gen_shri_i32(tmp, t0, 16);
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tcg_gen_andi_i32(tmp, tmp, 0xff);
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tcg_gen_or_i32(t1, rm, tmp);
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tcg_gen_mov_i32(t0, rd);
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dead_tmp(tmp);
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dead_tmp(rm);
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dead_tmp(rd);
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}
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static void gen_neon_zip_u16(TCGv t0, TCGv t1)
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static int gen_neon_zip(int rd, int rm, int size, int q)
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{
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TCGv tmp, tmp2;
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tmp = new_tmp();
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tmp2 = new_tmp();
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tcg_gen_andi_i32(tmp, t0, 0xffff);
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tcg_gen_shli_i32(tmp2, t1, 16);
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tcg_gen_or_i32(tmp, tmp, tmp2);
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tcg_gen_andi_i32(t1, t1, 0xffff0000);
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tcg_gen_shri_i32(tmp2, t0, 16);
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tcg_gen_or_i32(t1, t1, tmp2);
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tcg_gen_mov_i32(t0, tmp);
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dead_tmp(tmp2);
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dead_tmp(tmp);
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if (size == 3 || (!q && size == 2)) {
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return 1;
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}
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tmp = tcg_const_i32(rd);
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tmp2 = tcg_const_i32(rm);
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if (q) {
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switch (size) {
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case 0:
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gen_helper_neon_qzip8(cpu_env, tmp, tmp2);
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break;
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case 1:
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gen_helper_neon_qzip16(cpu_env, tmp, tmp2);
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break;
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case 2:
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gen_helper_neon_qzip32(cpu_env, tmp, tmp2);
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break;
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default:
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abort();
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}
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} else {
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switch (size) {
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case 0:
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gen_helper_neon_zip8(cpu_env, tmp, tmp2);
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break;
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case 1:
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gen_helper_neon_zip16(cpu_env, tmp, tmp2);
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break;
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default:
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abort();
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}
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}
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp2);
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return 0;
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}
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static void gen_neon_trn_u8(TCGv t0, TCGv t1)
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@ -5429,29 +5413,8 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
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}
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break;
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case 35: /* VZIP */
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/* Reg Before After
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Rd A3 A2 A1 A0 B1 A1 B0 A0
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Rm B3 B2 B1 B0 B3 A3 B2 A2
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*/
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if (size == 3)
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if (gen_neon_zip(rd, rm, size, q)) {
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return 1;
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count = (q ? 4 : 2);
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for (n = 0; n < count; n++) {
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tmp = neon_load_reg(rd, n);
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tmp2 = neon_load_reg(rd, n);
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switch (size) {
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case 0: gen_neon_zip_u8(tmp, tmp2); break;
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case 1: gen_neon_zip_u16(tmp, tmp2); break;
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case 2: /* no-op */; break;
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default: abort();
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}
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neon_store_scratch(n * 2, tmp);
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neon_store_scratch(n * 2 + 1, tmp2);
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}
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for (n = 0; n < count * 2; n++) {
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int reg = (n < count) ? rd : rm;
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tmp = neon_load_scratch(n);
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neon_store_reg(reg, n % count, tmp);
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}
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break;
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case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
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