mirror of https://github.com/proxmox/mirror_qemu
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
parent
16c38f36f5
commit
d7a4fcb034
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@ -64,32 +64,6 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
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return do_grev(rs1, rs2, 32);
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}
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static target_ulong do_gorc(target_ulong rs1,
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target_ulong rs2,
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int bits)
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{
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target_ulong x = rs1;
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int i, shift;
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for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
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if (rs2 & shift) {
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x |= do_swap(x, adjacent_masks[i], shift);
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}
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}
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return x;
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}
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target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
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{
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return do_gorc(rs1, rs2, TARGET_LONG_BITS);
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}
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target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
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{
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return do_gorc(rs1, rs2, 32);
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}
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target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
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{
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target_ulong result = 0;
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@ -61,8 +61,6 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
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/* Bitmanip */
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DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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@ -681,6 +681,7 @@ max 0000101 .......... 110 ..... 0110011 @r
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maxu 0000101 .......... 111 ..... 0110011 @r
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min 0000101 .......... 100 ..... 0110011 @r
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minu 0000101 .......... 101 ..... 0110011 @r
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orc_b 001010 000111 ..... 101 ..... 0010011 @r2
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orn 0100000 .......... 110 ..... 0110011 @r
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rol 0110000 .......... 001 ..... 0110011 @r
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ror 0110000 .......... 101 ..... 0110011 @r
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@ -702,19 +703,14 @@ pack 0000100 .......... 100 ..... 0110011 @r
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packu 0100100 .......... 100 ..... 0110011 @r
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packh 0000100 .......... 111 ..... 0110011 @r
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grev 0110100 .......... 101 ..... 0110011 @r
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gorc 0010100 .......... 101 ..... 0110011 @r
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grevi 01101. ........... 101 ..... 0010011 @sh
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gorci 00101. ........... 101 ..... 0010011 @sh
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# *** RV64B Standard Extension (in addition to RV32B) ***
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packw 0000100 .......... 100 ..... 0111011 @r
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packuw 0100100 .......... 100 ..... 0111011 @r
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grevw 0110100 .......... 101 ..... 0111011 @r
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gorcw 0010100 .......... 101 ..... 0111011 @r
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greviw 0110100 .......... 101 ..... 0011011 @sh5
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gorciw 0010100 .......... 101 ..... 0011011 @sh5
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# *** RV32 Zbc Standard Extension ***
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clmul 0000101 .......... 001 ..... 0110011 @r
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@ -295,16 +295,27 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
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}
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static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
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static void gen_orc_b(TCGv ret, TCGv source1)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
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TCGv tmp = tcg_temp_new();
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TCGv ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
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/* Set lsb in each byte if the byte was zero. */
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tcg_gen_sub_tl(tmp, source1, ones);
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tcg_gen_andc_tl(tmp, tmp, source1);
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tcg_gen_shri_tl(tmp, tmp, 7);
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tcg_gen_andc_tl(tmp, ones, tmp);
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/* Replicate the lsb of each byte across the byte. */
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tcg_gen_muli_tl(ret, tmp, 0xff);
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tcg_temp_free(tmp);
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}
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static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
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static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
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REQUIRE_ZBB(ctx);
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return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
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}
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#define GEN_SHADD(SHAMT) \
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@ -476,22 +487,6 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
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}
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static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
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}
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static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
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}
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#define GEN_SHADD_UW(SHAMT) \
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static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
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{ \
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