mirror of https://github.com/proxmox/mirror_qemu
hw/cxl/rp: Add a root port
This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to a specific CXL host bridge. For example: -device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4 Like the host bridge patch, the ACPI tables aren't generated at this point and so system software cannot use it. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>master
Ben Widawsky
Michael S. Tsirkin
parent
33c47ab967
commit
d86d30192b
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@ -27,3 +27,8 @@ config DEC_PCI
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config SIMBA
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bool
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config CXL
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bool
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default y if PCI_EXPRESS && PXB
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depends on PCI_EXPRESS && MSI_NONBROKEN && PXB
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@ -0,0 +1,236 @@
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/*
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* CXL 2.0 Root Port Implementation
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/range.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "hw/cxl/cxl.h"
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#define CXL_ROOT_PORT_DID 0x7075
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/* Copied from the gen root port which we derive */
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#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
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#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
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(GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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#define CXL_ROOT_PORT_DVSEC_OFFSET \
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(GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF)
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typedef struct CXLRootPort {
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/*< private >*/
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PCIESlot parent_obj;
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CXLComponentState cxl_cstate;
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PCIResReserve res_reserve;
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} CXLRootPort;
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#define TYPE_CXL_ROOT_PORT "cxl-rp"
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DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT)
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static void latch_registers(CXLRootPort *crp)
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{
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uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers;
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uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask;
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cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
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}
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static void build_dvsecs(CXLComponentState *cxl)
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{
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uint8_t *dvsec;
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dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
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cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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EXTENSIONS_PORT_DVSEC_LENGTH,
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EXTENSIONS_PORT_DVSEC,
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EXTENSIONS_PORT_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECPortGPF){
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.rsvd = 0,
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.phase1_ctrl = 1, /* 1μs timeout */
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.phase2_ctrl = 1, /* 1μs timeout */
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};
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cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC,
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GPF_PORT_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
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.cap = 0x26, /* IO, Mem, non-MLD */
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.ctrl = 0x2,
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.status = 0x26, /* same */
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.rcvd_mod_ts_data_phase1 = 0xef,
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};
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cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
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PCIE_FLEXBUS_PORT_DVSEC,
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PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
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.rsvd = 0,
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.reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
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.reg0_base_hi = 0,
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};
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cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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REG_LOC_DVSEC_REVID, dvsec);
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}
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static void cxl_rp_realize(DeviceState *dev, Error **errp)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
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CXLRootPort *crp = CXL_ROOT_PORT(dev);
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CXLComponentState *cxl_cstate = &crp->cxl_cstate;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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MemoryRegion *component_bar = &cregs->component_registers;
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Error *local_err = NULL;
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rpc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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int rc =
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pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, errp);
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if (rc < 0) {
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rpc->parent_class.exit(pci_dev);
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return;
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}
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if (!crp->res_reserve.io || crp->res_reserve.io == -1) {
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pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND,
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PCI_COMMAND_IO);
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pci_dev->wmask[PCI_IO_BASE] = 0;
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pci_dev->wmask[PCI_IO_LIMIT] = 0;
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}
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cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET;
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cxl_cstate->pdev = pci_dev;
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build_dvsecs(&crp->cxl_cstate);
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cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
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TYPE_CXL_ROOT_PORT);
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pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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component_bar);
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}
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static void cxl_rp_reset(DeviceState *dev)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
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CXLRootPort *crp = CXL_ROOT_PORT(dev);
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rpc->parent_reset(dev);
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latch_registers(crp);
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}
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static Property gen_rp_props[] = {
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DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1),
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DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1),
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DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref, -1),
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DEFINE_PROP_SIZE("pref32-reserve", CXLRootPort, res_reserve.mem_pref_32,
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-1),
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DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64,
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-1),
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DEFINE_PROP_END_OF_LIST()
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};
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static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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CXLRootPort *crp = CXL_ROOT_PORT(dev);
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if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
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uint8_t *reg = &dev->config[addr];
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addr -= crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
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if (addr == PORT_CONTROL_OFFSET) {
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if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
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/* unmask SBR */
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qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
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}
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if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
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/* Alt Memory & ID Space Enable */
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qemu_log_mask(LOG_UNIMP,
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"Alt Memory & ID space is not supported\n");
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}
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}
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}
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}
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static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
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int len)
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{
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uint16_t slt_ctl, slt_sta;
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pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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cxl_rp_dvsec_write_config(d, address, val, len);
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}
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static void cxl_root_port_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = CXL_ROOT_PORT_DID;
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dc->desc = "CXL Root Port";
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k->revision = 0;
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device_class_set_props(dc, gen_rp_props);
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k->config_write = cxl_rp_write_config;
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device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
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device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset);
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rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
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rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
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dc->hotpluggable = false;
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}
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static const TypeInfo cxl_root_port_info = {
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.name = TYPE_CXL_ROOT_PORT,
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.parent = TYPE_PCIE_ROOT_PORT,
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.instance_size = sizeof(CXLRootPort),
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.class_init = cxl_root_port_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CXL_DEVICE },
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{ }
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},
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};
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static void cxl_register(void)
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{
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type_register_static(&cxl_root_port_info);
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}
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type_init(cxl_register);
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@ -5,6 +5,7 @@ pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c'))
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pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pcie_root_port.c', 'pcie_pci_bridge.c'))
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pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'))
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pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c'))
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pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
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# NewWorld PowerMac
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pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
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@ -67,7 +67,11 @@ static void rp_realize(PCIDevice *d, Error **errp)
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int rc;
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pci_config_set_interrupt_pin(d->config, 1);
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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if (d->cap_present & QEMU_PCIE_CAP_CXL) {
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pci_bridge_initfn(d, TYPE_CXL_BUS);
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} else {
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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}
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pcie_port_init_reg(d);
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rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,
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@ -2762,7 +2762,9 @@ static void pci_device_class_base_init(ObjectClass *klass, void *data)
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object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
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ObjectClass *pcie =
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object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
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assert(conventional || pcie);
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ObjectClass *cxl =
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object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE);
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assert(conventional || pcie || cxl);
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}
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}
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