mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: fix TLB flush instructions
According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
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dcd82c118c
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dbb1fb277c
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@ -1801,12 +1801,17 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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}
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}
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/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
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* Page D4-1736 (DDI0487A.b)
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*/
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static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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{
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/* Invalidate by VA (AArch64 version) */
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/* Invalidate by VA (AArch64 version) */
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint64_t pageaddr = value << 12;
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page(CPU(cpu), pageaddr);
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tlb_flush_page(CPU(cpu), pageaddr);
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}
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}
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@ -1815,7 +1820,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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{
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/* Invalidate by VA, all ASIDs (AArch64 version) */
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/* Invalidate by VA, all ASIDs (AArch64 version) */
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint64_t pageaddr = value << 12;
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page(CPU(cpu), pageaddr);
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tlb_flush_page(CPU(cpu), pageaddr);
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}
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}
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