mirror of https://github.com/proxmox/mirror_qemu
hw/arm/aspeed: Check for CPU types in machine_run_board_init()
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).
Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU is invalid (see commit
e702cbc19e
("machine: Improve is_cpu_type_supported()").
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
master
parent
d815649c51
commit
dc13909ed0
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@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
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mc->default_cpus = sc->num_cpus;
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mc->default_cpus = sc->num_cpus;
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mc->min_cpus = sc->num_cpus;
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mc->min_cpus = sc->num_cpus;
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mc->max_cpus = sc->num_cpus;
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mc->max_cpus = sc->num_cpus;
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mc->valid_cpu_types = sc->valid_cpu_types;
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}
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}
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static void aspeed_machine_class_init(ObjectClass *oc, void *data)
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static void aspeed_machine_class_init(ObjectClass *oc, void *data)
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@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
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static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
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static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
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{
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
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NULL
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};
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DeviceClass *dc = DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
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dc->realize = aspeed_soc_ast1030_realize;
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dc->realize = aspeed_soc_ast1030_realize;
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sc->name = "ast1030-a1";
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sc->name = "ast1030-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST1030_A1_SILICON_REV;
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sc->silicon_rev = AST1030_A1_SILICON_REV;
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sc->sram_size = 0xc0000;
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sc->sram_size = 0xc0000;
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sc->secsram_size = 0x40000; /* 256 * KiB */
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sc->secsram_size = 0x40000; /* 256 * KiB */
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@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
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static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
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{
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("arm926"),
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NULL
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};
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
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dc->user_creatable = false;
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dc->user_creatable = false;
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sc->name = "ast2400-a1";
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sc->name = "ast2400-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2400_A1_SILICON_REV;
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sc->silicon_rev = AST2400_A1_SILICON_REV;
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sc->sram_size = 0x8000;
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sc->sram_size = 0x8000;
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sc->spis_num = 1;
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sc->spis_num = 1;
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@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
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{
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("arm1176"),
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NULL
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};
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
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dc->user_creatable = false;
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dc->user_creatable = false;
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sc->name = "ast2500-a1";
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sc->name = "ast2500-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2500_A1_SILICON_REV;
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sc->silicon_rev = AST2500_A1_SILICON_REV;
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sc->sram_size = 0x9000;
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sc->sram_size = 0x9000;
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sc->spis_num = 2;
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sc->spis_num = 2;
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@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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{
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-a7"),
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NULL
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};
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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dc->realize = aspeed_soc_ast2600_realize;
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dc->realize = aspeed_soc_ast2600_realize;
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sc->name = "ast2600-a3";
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sc->name = "ast2600-a3";
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
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sc->valid_cpu_types = valid_cpu_types;
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sc->silicon_rev = AST2600_A3_SILICON_REV;
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sc->silicon_rev = AST2600_A3_SILICON_REV;
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sc->sram_size = 0x16400;
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sc->sram_size = 0x16400;
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sc->spis_num = 2;
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sc->spis_num = 2;
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@ -20,7 +20,10 @@
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const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
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const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
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{
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{
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return sc->cpu_type;
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assert(sc->valid_cpu_types);
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assert(sc->valid_cpu_types[0]);
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assert(!sc->valid_cpu_types[1]);
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return sc->valid_cpu_types[0];
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}
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}
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
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@ -128,7 +128,8 @@ struct AspeedSoCClass {
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DeviceClass parent_class;
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DeviceClass parent_class;
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const char *name;
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const char *name;
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const char *cpu_type;
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/** valid_cpu_types: NULL terminated array of a single CPU type. */
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const char * const *valid_cpu_types;
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uint32_t silicon_rev;
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uint32_t silicon_rev;
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uint64_t sram_size;
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uint64_t sram_size;
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uint64_t secsram_size;
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uint64_t secsram_size;
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