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aspeed: move the flash module mapping address under the controller definition 

This will ease the definition of the new controllers for the AST2500
SoC and also ease the support of the segment registers, which provide
a way to reconfigure the mapping window of each slave.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1474977462-28032-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Cédric Le Goater 2016-10-17 19:22:16 +01:00 committed by Peter Maydell
parent 0e5803dfbc
commit dcb834447f
3 changed files with 17 additions and 10 deletions
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9
hw/arm/aspeed_soc.c
View File

@ -31,9 +31,6 @@
#define ASPEED_SOC_TIMER_BASE 0x1E782000
#define ASPEED_SOC_I2C_BASE 0x1E78A000
#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@ -187,7 +184,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SOC_FMC_FLASH_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
qdev_get_gpio_in(DEVICE(&s->vic), 19));
@ -200,7 +198,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
s->spi.ctrl->flash_window_base);
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);

15
hw/ssi/aspeed_smc.c
View File

@ -127,6 +127,10 @@
#define R_SPI_MISC_CTRL (0x10 / 4)
#define R_SPI_TIMINGS (0x14 / 4)
#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
/*
* Default segments mapping addresses and size for each slave per
* controller. These can be changed when board is initialized with the
@ -151,11 +155,14 @@ static const AspeedSegments aspeed_segments_spi[] = {
static const AspeedSMCController controllers[] = {
{ "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 },
CONF_ENABLE_W0, 5, aspeed_segments_legacy,
ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 },
{ "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 },
CONF_ENABLE_W0, 5, aspeed_segments_fmc,
ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 },
{ "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS,
SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 },
SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi,
ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 },
};
static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
@ -395,7 +402,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&s->mmio_flash, OBJECT(s),
&aspeed_smc_flash_default_ops, s, name,
s->ctrl->mapping_window_size);
s->ctrl->flash_window_size);
sysbus_init_mmio(sbd, &s->mmio_flash);
s->flashes = g_new0(AspeedSMCFlash, s->num_cs);

3
include/hw/ssi/aspeed_smc.h
View File

@ -42,7 +42,8 @@ typedef struct AspeedSMCController {
uint8_t conf_enable_w0;
uint8_t max_slaves;
const AspeedSegments *segments;
uint32_t mapping_window_size;
hwaddr flash_window_base;
uint32_t flash_window_size;
} AspeedSMCController;
typedef struct AspeedSMCFlash {