From df6adb68c1b1808f164c9ed8a04fe14d9c04e82c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 7 Dec 2020 22:33:22 +0100 Subject: [PATCH] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce cpu_supports_isa() which takes a CPUMIPSState argument, more useful at runtime when the CPU is created (no need to call the extensive object_class_by_name()). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-3-f4bug@amsat.org> --- target/mips/cpu.c | 5 +++++ target/mips/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..687e2680dd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) return MIPS_CPU(cpu); } + +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) +{ + return (env->cpu_model->insn_flags & isa_mask) != 0; +} diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c65c87bf9..e8bca75f23 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address);