From a68d82b8ad73ff3eea6356b000e1c68dc7acea51 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:01:46 -0700 Subject: [PATCH 1/8] target/alpha: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/helper.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 8a6a948572..57e2c212b3 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -442,20 +442,19 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i = 0; i < 31; i++) { - cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, - linux_reg_names[i], cpu_alpha_load_gr(env, i)); - if ((i % 3) == 2) - cpu_fprintf(f, "\n"); + cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i, + linux_reg_names[i], cpu_alpha_load_gr(env, i), + (i % 3) == 2 ? '\n' : ' '); } cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", env->lock_addr, env->lock_value); - for (i = 0; i < 31; i++) { - cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i, - *((uint64_t *)(&env->fir[i]))); - if ((i % 3) == 2) - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 31; i++) { + cpu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i], + (i % 3) == 2 ? '\n' : ' '); + } } cpu_fprintf(f, "\n"); } From 1cc5af6902cd646d91a7d590b365c87ba8909a72 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:14:30 -0700 Subject: [PATCH 2/8] target/mips: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Aurelien Jarno Cc: Yongbok Kim Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index f1c1fdd35c..e88f983ae7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20446,8 +20446,9 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, env->CP0_Config2, env->CP0_Config3); cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", env->CP0_Config4, env->CP0_Config5); - if (env->hflags & MIPS_HFLAG_FPU) + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { fpu_dump_state(env, f, cpu_fprintf, flags); + } } void mips_tcg_init(void) From 685f1ce236d93177532f5ec42b130a50809bf171 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:26:59 -0700 Subject: [PATCH 3/8] target/ppc: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Alexander Graf Cc: David Gibson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/translate.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d5e5f953da..e30d99fcbc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", env->reserve_addr); - for (i = 0; i < 32; i++) { - if ((i & (RFPL - 1)) == 0) - cpu_fprintf(f, "FPR%02d", i); - cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); - if ((i & (RFPL - 1)) == (RFPL - 1)) - cpu_fprintf(f, "\n"); + + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + if ((i & (RFPL - 1)) == 0) { + cpu_fprintf(f, "FPR%02d", i); + } + cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); + if ((i & (RFPL - 1)) == (RFPL - 1)) { + cpu_fprintf(f, "\n"); + } + } + cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); } - cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); + #if !defined(CONFIG_USER_ONLY) cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", From 86ea188012c26a724bfefe0fb9a838ce808993cc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:31:33 -0700 Subject: [PATCH 4/8] target/riscv: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Reviewed-by: Michael Clark Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e5a56d4e3..d630e8fd6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -219,11 +219,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, "\n"); } } - for (i = 0; i < 32; i++) { - cpu_fprintf(f, " %s %016" PRIx64, - riscv_fpr_regnames[i], env->fpr[i]); - if ((i & 3) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, " %s %016" PRIx64, + riscv_fpr_regnames[i], env->fpr[i]); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } } } } From af6e5ea28f0b59097a1215e8d063acbb71361b37 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:38:23 -0700 Subject: [PATCH 5/8] target/s390x: Honor CPU_DUMP_FPU Also do not dump both "fpu" and "vector" registers as the former overlaps the latter. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/helper.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/target/s390x/helper.c b/target/s390x/helper.c index e8548f340a..fd5791f134 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -327,21 +327,22 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - for (i = 0; i < 16; i++) { - cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + if (s390_has_feat(S390_FEAT_VECTOR)) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c", + i, env->vregs[i][0].ll, env->vregs[i][1].ll, + i % 2 ? '\n' : ' '); + } } else { - cpu_fprintf(f, " "); + for (i = 0; i < 16; i++) { + cpu_fprintf(f, "F%02d=%016" PRIx64 "%c", + i, get_freg(env, i)->ll, + (i % 4) == 3 ? '\n' : ' '); + } } } - for (i = 0; i < 32; i++) { - cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i, - env->vregs[i][0].ll, env->vregs[i][1].ll); - cpu_fprintf(f, (i % 2) ? "\n" : " "); - } - #ifndef CONFIG_USER_ONLY for (i = 0; i < 16; i++) { cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); From d13c394c754cd7d3c86a8968885ad6394d8d69ff Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:42:10 -0700 Subject: [PATCH 6/8] target/sparc: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Mark Cave-Ayland Cc: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ff6ed91f9a..0f090ece54 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -647,15 +647,18 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - for (i = 0; i < TARGET_DPREGS; i++) { - if ((i & 3) == 0) { - cpu_fprintf(f, "%%f%02d: ", i * 2); - } - cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); - if ((i & 3) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < TARGET_DPREGS; i++) { + if ((i & 3) == 0) { + cpu_fprintf(f, "%%f%02d: ", i * 2); + } + cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } } } + #ifdef TARGET_SPARC64 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, (unsigned)cpu_get_ccr(env)); From a651e033c6cae17d0d05902158d35ca6bf25eb5d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:44:33 -0700 Subject: [PATCH 7/8] target/unicore32: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Guan Xuetao Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/unicore32/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index abe2ea8592..3cae111955 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -2101,7 +2101,9 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f, psr & (1 << 28) ? 'V' : '-', cpu_mode_names[psr & 0xf]); - cpu_dump_state_ucf64(env, f, cpu_fprintf, flags); + if (flags & CPU_DUMP_FPU) { + cpu_dump_state_ucf64(env, f, cpu_fprintf, flags); + } } void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, From f29c0b170fa9e0568f2d02e764e18b00cad3a27f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 10 May 2018 20:46:23 -0700 Subject: [PATCH 8/8] target/xtensa: Honor CPU_DUMP_FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index ae0feb0254..53f6f5db8f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1243,7 +1243,8 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, } } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { + if ((flags & CPU_DUMP_FPU) && + xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { cpu_fprintf(f, "\n"); for (i = 0; i < 16; ++i) {